- Drive all frontend activities like synthesis, Lint, CDC, Formality, ECO, etc.
- Optimization for timing, area, power, performance etc.
- Develop micro-architecture from given architecture and algorithms
- RTL design, verification and integration
- Work closely with other teams like design, SoC, backend, etc.
- MS degree with at least five year's equivalent experience
- Expertise in synthesis, timing analysis and closure, Lint/CDC check, ECO, Formality
- Experience with scripting languages like Perl, Tcl or Python
- RTL logic design or implementation experience on multi-million gate ASICs
- Hands on experience in chip development process with proficiency in frontend tools and methodologies
- Good documentation and communication skill
Job Type: Full-time