Physical Design Engineer, University Graduate

Google - Mountain View, CA4.3

Full-time
Note: By applying to this position your application is automatically submitted to the following locations: Sunnyvale, CA, USA; Mountain View, CA, USA
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

As a Physical Design Engineer on the chip implementation team, you will work on the physical implementation of ASICs using advanced technology nodes. You will perform technical evaluations of vendors, process nodes and IP, while also providing recommendations. You will work with Architecture, Logic Design and associated teams to understand and implement their requirements. You will also drive block and full-chip level physical implementation and QOR (power, timing, area). In addition, you will develop physical design methodologies, automation scripts and write documentation.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We're always on call to keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities
Perform physical implementation steps including synthesis, floorplanning, place and route, power/clock distribution, congestion analysis, timing closure, CDC analysis and formal verification.
Work with logic designers to drive architectural feasibility studies, to develop timing, power and area design targets, and to explore RTL/design tradeoffs for physical design closure.
Perform technical evaluations of vendors, process nodes and IP, and provide recommendations accordingly.
Develop physical design methodologies and automation scripts for various implementation steps.
Qualifications

Minimum qualifications:
Bachelor's degree in Electrical Engineering or related field, or equivalent practical experience.
Experience in leading one or more aspects of physical design.
Experience with scripting in Python, TCL, VHDL, Go and/or Perl.
Authorization to work in the United States

Preferred qualifications:
Master's or Doctorate degree in Electrical Engineering or related field.
Experience in leading one or more aspects of physical design.
Experience in IP integration (e.g. memories, IO’s and Analog IP, etc.).
Experience in solving physical design challenges across various technologies (e.g. embedded processors, DDR, networking fabrics, etc.).
Experience in extraction of design parameters, QOR metrics, and in analyzing trends.
Working knowledge of Verilog/SystemVerilog.
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