Full Job Description
Bachelor's degree in Electrical Engineering, Computer Engineering, related field, or equivalent practical experience.
5 years of relevant work experience.
Experience with low power design techniques, power gating, multi-voltage designs, UPF/CPF and chip power management.
Experience with advanced foundry process nodes and FinFET based designs.
Familiar with complex SoC chip implementation, e.g. physical design, chip top level, IP integration, layout, EDA tools, timing optimizations, EM/IR analysis.
Strong written and oral communications skills with the ability to influence others with your technical visions and with an attention to detail.
Demonstrated self-learning, leadership skills and a growth mindset throughout your career.
About the job
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
As a chip and design IP technologist, you will work closely with wafer foundries to shape and influence CMOS transistor and SRAM performance and co-develop with the IP ecosystem. Additionally, you will perform technical simulations and evaluations of foundry CMOS process nodes, custom or semi-custom circuit library and memory designs, mixed-signal and analog circuit peripherals, and sensors. You will also provide technical leadership in chip interface and controller IPs evaluation, working with IP vendors and commercial teams to define third-party IP strategy while driving complex IP subsystem design integration from concept/planning through to execution and bring-up.
In this role, you will manage vendor collateral requirements, track issues, and drive resolutions with your leadership skills, while collaborating with teams across Google to identify and create strategic opportunities for innovation to deliver high systems impact.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Work with architecture and micro-architecture teams to define clocking architecture and circuitry implementations and requirements.
Perform technical evaluations on clocking IP vendor designs and implementations and/or custom sensor circuits and provide recommendations.
Lead chip top level verification and modeling of analog/mixed signal IPs.
Design and integrate circuits IP from modeling, simulations, layout to bench testing and ATE characterization. Conduct timing analysis and flows for clocking network designs.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing this form.