At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence Design Systems is looking for a highly motivated computer engineer to work with the Modus R&D engineering team in the Front-End Design business unit. You will be part of a team responsible for designing, developing, debugging and supporting Automatic Test Pattern Generation (ATPG) software. Development responsibilities will include supporting cell-aware faulting flow development and deployment, test point insertion algorithm development and results optimization, and general ATPG software development
The successful candidate will possess the following combination of education and experience:
BS/MS in Computer Science or Computer Engineering or Electrical Engineering
Excellent digital logic design skills
Experience with cell-aware fault modelling flows and deployment
Excellent C/C++ programming and software engineering skills
Excellence in algorithm and data structure design
Experience with UNIX and/or LINUX platforms is preferred
Strong knowledge of Tcl o r Perl is preferred
Strong ability to learn
Strong analysis and problem solving skills
Prior experience with large hardware or software development projects is highly recommended
Good communication skill is preferred as the development team is distributed
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