Digital Designer

Elite Technical Services, Inc. - Rochester, MN4.6

Full-timeEstimated: $79,000 - $110,000 a year
Our client, the Special Purpose Processor Development Group (SPPDG) in Rochester, MN has an immediate need for a Digital Design Engineer to work with their engineering team to apply novel EDA methodologies developing a digital ASIC. The research team is dedicated to developing next generation electronics technology for high clock rate data and signal processor applications, high center-frequency and wide bandwidth analog and mixed-signal systems including the miniaturization and ruggedization of some of these systems.

This is work that matters. Help solve what others can't. Are you interested in learning more? Are you Digital Design Engineer experienced with full ASIC design, Cadence tool suite, flow and ancillary skills?

If so, for immediate consideration contact Elite Technical by hitting APPLY NOW or by calling 1 (800) 354-8350 (800-ELITE-50).


Required Skills
(1) Per client requirements must be a US Citizen able to pass an extensive background investigation
(2) BS/MS in EE/CS
(3) 6+ years of hands-on physical design and verification.
(4) Experienced with ASIC design flow, hierarchical physical design strategies, methodologies, and understand deep sub-micron technology issues
(5) Solid knowledge on Low Power Design, DFT, static timing analysis and closure, data skew balancing, duty cycle adjustment, EM/IR-Drop/crosstalk analysis, formal verification, physical verification, DFM.
(6) Extensive experience with Cadence tool suite for full-chip design, including:
  • Genus (formerly RTL compiler) - used to synthesize Behavioral RTL to Verilog Mapped Gates RTL
  • Innovus (formerly Encounter) - physical design, including chip image and place and route of digital gates
  • Tempus - timing signoff
  • Virtuoso - custom physical layout
(7) Experience with the following programming languages preferred:
  • Stylus - Common user interface for cadence physical design tools
  • Legacy Encounter
  • YAML - Used as part of the Stylus flow
  • Python
  • Verilog