SeeDevice Inc.- La Palma,Orange County, CA
See Device is a start-up Quantum Image Sensor company developing disruptive technology for precision photo detectors. Combining quantum mechanics based pixel technology with state-of-the-art CMOS mixed-signal chips, we develop innovative technology our clients utilize to actualize next generation, cutting-edge devices of the future, bringing them to the global market.
Digital design engineers will support the needs of the CMOS image sensor chip design team, executing on an aggressive roadmap to develop an ultra-sensitive, high performance CMOS quantum-sensor chip for global commercial deployment in bio-medical, mobile, machine vision/imaging, automotive, security, gaming, TOF, and consumer electronic device applications.
Digital design engineers will work under the direction of the CTO, and work closely with global teams of engineers, as key members of the hardware development team. Primary responsibilities will consist of the design, development, simulation, performance optimization and layout of subsystems of the CMOS sensor chips.
Specific responsibilities include:
Understand the overall application of the chip, proposing and developing improvements in overall design.
Design and document one or more blocks of an ASIC, including functionality and timing.
Implement designs in RTL (System Verilog, Chisel or other HDLs).
Create simple test benches and debug complex logic simulations.
Work closely with analog teams on functionality, interfaces, and documentation.
Documentation and analysis of chip design, simulation/layout, and test results of sensor and circuit performance
Perform full block design including RTL design, incorporation of analog blocks, place, route, verification, and reliability analysis
Work within a group of Image Sensor design experts and be assigned to a sensor product team; interface with design management and module design teams to create the detailed specification, report design progress, and to collect, track, and resolve any performance and circuit design issues.
Preparation of materials for company presentations
MS + 2 years of experience in industry involving high-performance digital or mixed-signal IC development in advanced CMOS processes
Good knowledge of Verilog RTL coding including state machines, adders, multipliers, combinatorial logic, etc
Good understanding of digital design for mixed signal control loops and designing Verilog code to control analog circuits (e.g. digital backend for ADC, digital PLL, etc)
Familiarity with behavioral Verilog code, including wreals
Ability to write thorough testbenches
Preferred knowledge of synthesis tool
Basic understanding of SystemVerilog and assertions preferred
Familiarity with place and route tool flow preferred
MATLAB understanding would be preferred
Deep understanding of constraints, especially for mixed-signal designs, including multiple clock domains and clock gating
Familiarity with timing closure and static timing analysis tools
Experience with scan chain vector generation and verification
Familiarity with Cadence Virtuoso required
Deep understanding of mixed power processes including design and limitations
Authorized to work in the U.S.
Able to travel worldwide without any restrictions
Job Type: Full-time
Education; Master's high preferred with 2 years of experience in industry
EQUAL OPPORTUNITY EMPLOYER:
The SeeDevice Inc. in conformity with applicable laws is an Equal Opportunity Employer and does not discriminate on the basis of race, color, sex, sexual orientation, age, religion, national origin, or disability.