ASIC Physical Design Engineering Tech Lead & Manager

Google - Mountain View, CA (30+ days ago)4.3


Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As an ASIC Physical Design Engineering Tech Lead & Manager, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

Pulling on your technical and leadership expertise, you lead end-to-end research projects in multiple areas of expertise across data center facilities and manage a team of direct reports working on equipment installation, troubleshooting and debugging.

You will be part of Google’s Consumer Hardware Silicon team, developing high performance and low power hardware to enable Google’s continuous innovations in mobile. This is a highly technical leadership position. You will be leading all aspects of physical design for Application Specific Integrated Circuits (ASIC) in advanced technology nodes, including physical synthesis, floor planning, place and route, STA, DRC, LVS, LEC, DVFS, IR/EM sign-off, and DFT. You will lead the team that performs block and full-chip level physical implementation and QoR (power, timing, area), as well as setting methodologies and flows.

Google's mission is to organize the world's information and make it universally accessible and useful. Our Hardware team researches, designs, and develops new technologies and hardware to make our user's interaction with computing faster, more powerful, and seamless. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, our Hardware team is making people's lives better through technology.

Responsibilities
  • Work with architects, logic designers and ASIC vendors to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs for physical design closure.
  • Work with logic verification, and software teams to understand and implement the design requirements for clocking and power management.

Qualifications Minimum qualifications:
  • Bachelor's degree or equivalent practical experience.
  • Multiple foundry experience.
  • Experience in leading implementation, flows and/or methodology for building complex SoC with 100 million plus gates in advanced nodes. Experience in people leadership
  • Experience in ASIC vendor management and in IP integration (memories, FLASH, IO’s and Analog IP)

Preferred qualifications:
  • Experience setting flows and methodologies for physical design and design sign off
  • Hands on experience and a solid understanding in all of the following physical design flows and methodologies: synthesis, place and route, STA, formal verification, CDC and power/EM/IR analysis, power intent (UPF/CPF), DFT.
  • Hands on experience and a solid understanding in most or all of the following tools: Design Compiler, ICC/ICC2, Innovus/EDI, Primetime, Conformal LEC and CLP, Spyglass and Power Artist, DRC tools such as Calibre, DFT Compiler/Tessent/Encounter Test, Electrical Analysis tools such as Redhawk/Voltus
  • Proficiency in semiconductor device physics and transistor characteristics.

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