Bachelor's degree in Electrical Engineering or equivalent practical experience.
7 years of experience with physical design in advanced process nodes and shipping ASICs.
Experience in chip development processes (e.g., IP selection, logic design, synthesis, floorplanning, clocking, timing, place and route, static timing analysis, power integrity, LEC and physical verification).
Experience leading one or more aspects of physical design.
Experience in IP integration (e.g., memories, IO’s, and Analog IP).
Experience solving physical design challenges for complex designs.
Experience in extraction of design parameters, QOR metrics, and analyzing trends.
Demonstrated understanding of semiconductor device physics, transistor characteristics, and Verilog/System Verilog.
About the job
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
As a Physical Design Engineer, you will work on a wide variety of physical design and implementation challenges such as synthesis, floor planning, place and route, clocking, timing, power, LEC and IP integration within a small team. Our projects exists at the intersection of Machine Learning and hardware. We are resourceful and innovate and move fast. In this role, You will help resolve interesting challenges while working with new and exciting technology.
There is always more information out there, and the Research and Machine Intelligence team has a never-ending quest to find it and make it accessible. We're constantly refining our signature search engine to provide better results, and developing offerings like Google Instant, Google Voice Search and Google Image Search to make it faster and more engaging. We're providing users around the world with great search results every day, but at Google, great just isn't good enough. We're just getting started.
Perform physical implementation steps including synthesis, floor planning, place and route, power/clock distribution, congestion analysis, timing closure, CDC analysis, and formal verification.
Work with logic designers to drive architectural feasibility studies, develop timing, power and area design goals, and explore RTL/design tradeoffs for physical design closure.
Perform technical evaluations of vendors, process nodes, and IP and provide recommendations.
Develop physical design methodologies and automation scripts for various implementation steps.
Collaborate with teams across Google to develop ideas for high impact ASIC and hardware projects.
At Google, we don’t just accept difference—we celebrate it, we support it, and we thrive on it for the benefit of our employees, our products and our community. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing this form.