Physical Design CAD Automation Engineer, Consumer Hardware

Google - Mountain View, CA (30+ days ago)4.3


Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery. cutting-edge data centers affecting millions of Google users.

You will be part of Google’s Consumer Hardware Silicon team, developing high performance and low power flows to enable Google’s continuous innovations in mobile hardware.

Google's mission is to organize the world's information and make it universally accessible and useful. Our Hardware team researches, designs, and develops new technologies and hardware to make our user's interaction with computing faster, more powerful, and seamless. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, our Hardware team is making people's lives better through technology.

Responsibilities
  • Develop and use physical design methodologies and automation scripts, and write documentation. Perform technical evaluations of vendors, process nodes and IP, and provide recommendations.
  • Work with architects, logic and physical designers to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs for automated physical design closure. Work with logic design, verification, and software teams to understand the design requirements for clocking and power management.
  • Develop all aspects of Application Specific Integrated Circuit (ASIC) implementation, with emphasis on physical synthesis, design for testability, place and route, static timing analysis, Verilog generator, third-party IP integration, DVFS, advanced technology nodes.
  • Drive block implementation flow automation and QOR (power, timing, area).

Qualifications Minimum qualifications:
  • 4 years of experience in ASIC physical design. Experience in some of the following physical design flows and methodologies: synthesis, place and route, STA, DFT, formal verification, CDC, and power analysis, power intent (UPF/CPF), IR/EM analysis.
  • Experience in some of the following tools: Design Compiler, ICC/ICC2, Innovus/EDI, Primetime, Conformal LEC and CLP, Spyglass and Power Artist, DRC tools such as Calibre, DFT Compiler/Tessent/Encounter Test, Electrical Analysis tools such as Redhawk/Voltus.
  • Scripting experience in Python, Tcl and/or Perl.
  • Experience with semiconductor device physics and transistor characteristics.

Preferred qualifications:
  • 6 years of experience in ASIC physical design flows and methodologies in 7nm - 40nm process nodes.
  • Experience leading one or more aspects of physical design or physical design flow/methodology, to successful tapeouts and shipping silicon.
  • Multiple foundry experience.
  • Experience in extraction of design parameters, QoR metrics, and analyzing trends.
  • Experience and/or knowledge in high level synthesis (HLS).

At Google, we don’t just accept difference - we celebrate it, we support it, and we thrive on it for the benefit of our employees, our products and our community. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you have a disability or special need that requires accommodation, please let us know.

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