The Reconfigurable Computing Group at the University of Southern California’s Information Sciences Institute is a long-time pioneer of research investigating Field Programmable Gate Arrays. Spanning the days of homogeneous logic devices to today’s billion transistor System on Chip devices, RCG has led the way from being the first to implement application level partial runtime reconfiguration, investigating 3D FPGA architectures, developing Autonomous System on Chip architectures, releasing open source CAD tools which target real physical devices, IP to address software / hardware co-design complexity and continues today with research ranging from developing programming models for next generation industry devices to conducting experiments on the International Space Station. Today, RCG is addressing our nation’s challenges in big data, hardware cybersecurity, trusted systems, cognitive radio and more.
USC/ISI is looking for highly talented, motivated researchers to lead and impact state of the art research and development in the area of reconfigurable computing. This position will lead development for custom internal tools which target FPGA and ASIC front end design. These tools solve challenging problems in hardware security, high level abstraction for hardware design, and machine learning acceleration for critical systems. Realize effectiveness of solutions on physical FPGAs and custom ASIC fabrication. Lead development while contributing to advanced research, collaborating with peers within the group and across ISI, and contributing to publications in top tier conferences.
Qualified candidates for this position must be willing and eligible to apply for a collateral Secret clearance. Per U.S. government regulations, eligibility for this clearance requires U.S. citizenship. Current SECRET clearance or higher is a plus.
MS in Computer Engineering, Electrical Engineering, or Computer Science required.
Three years of experience designing, developing, implementing, and debugging firmware for FPGAs, including Xilinx Virtex7 or later architectures.
Three years of C++/Java and Python development experience, including contributions to large-scale software projects, commercial or open-source.
Solid understanding of CAD algorithms including synthesis, partitioning, mapping, placing, and routing.
Expert level use of Xilinx or Intel FPGA implementation tools, including High level synthesis.
Detailed understanding of mapped and unmapped netlist formats, such as EDIF, XDL, and structural Verilog.
Experience with Partial Runtime Reconfiguration and knowledge of FPGA bitstream formats a strong plus.
Experience with Torc, ABC, VPR, VTR, RapidSmith, GoAhead, or similar tools a plus.
Experience with Amazon EC2 F1 instances or related FPGA-based cloud platforms.
Experience with multi-processor system-on-chip, embedded systems software (Linux, cross-compilers) and Python productivity for FPGAs (i.e. Pynq).
Previous publications, patents, or innovations related to FPGA productivity, CAD or EDA algorithms and tools.
The University of Southern California values diversity and is committed to equal opportunity in employment.
Minimum Education: Master's degree, Combined work experience and education as equivalent Minimum Experience: 1 year Minimum Field of Expertise: Demonstrated creativity and innovation in solving conceptual programming problems. Competent to work independently on complex programming.