SOC DFT Engineer - 68794

Advanced Micro Devices, Inc. - Austin, TX3.8

Full-timeEstimated: $100,000 - $140,000 a year
EducationSkills
What you do at AMD changes everything

At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center.

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

Advanced Micro Devices, Inc. (NYSE: AMD) is an innovative technology company dedicated to collaborating with customers and technology partners to ignite the next generation of computing and graphics solutions at work, home and play. The world's top companies depend on AMD. We power everything from the Microsoft Xbox One and the Sony PlayStation 4, to powerful desktops and Windows 10-based laptops, 5K iMacs, the MacBook Pro and beyond. Our employees thrive on challenge and aren't afraid to test limits. Together, they drive the innovations that break the barriers of technology. As a member of the Semi-Custom Business Unit within AMD, your execution will help bring to life customers' special requirements for designs to be used in a broad range of products, from tablets to gaming consoles to servers and more. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.

Description of Duties:
As DFT engineer, your responsibilities are:
Implementation and verification of DFT architecture and features
Scan/Jtag/boundary scan insertion and ATPG pattern generation
Memory BIST logic generation, implementation and verification
ATPG patterns verification with gate level simulation
Test coverage and test cost reduction analysis
Post silicon support to ensure successful bringup and enhance yield learning

Skills required:
Masters in CS/EE with relevant course work and project background with 2+ years of experience, or Bachelors with 3+ years of experience
Excellent oral, written and interpersonal communication skills
Understanding of Design For Test methodologies is a plus
Experience with VCS simulation tool, Perl/Shell scripting and Verilog RTL design is a plus
Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX is a plus

Requisition Number: 68794
Country: United States State: Texas City: Austin
Job Function: Design

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