Top 504 Field programmable gate array Jobs in Milpitas, Ca

Principal Applied Scientist, ML Codesign
Amazon.com Services LLC —Sunnyvale, CA
- $228,700 - $309,400 a year
- Full-time
- Computer science
- 8 years
- Fair chance
- AD&D insurance
- Health insurance
13d
Hardware Design Engineer
Maxonic, Inc. —Milpitas, CA
- $148,000 - $245,000 a year
- Full-time
- Mid-level
- In-person
Quick Apply
4d
Senior Hardware Design Engineer – High Speed Boards
TMP Worldwide India Private Limited for ERS US —San Jose, CA
- $83,000 - $128,000 a year
- Email
- 7 years
- Mentoring
- In-person
- AD&D insurance
- Paid holidays
Quick Apply
Labview Engineer
TMP Worldwide India Private Limited for ERS US —Milpitas, CA
- $71,000 - $108,000 a year
- Email
- 8 years
- Bachelor's degree
- In-person
- AD&D insurance
- Paid holidays
Quick Apply
Design Verification Engineer
eTeam Inc. —San Jose, CA
- $150,000 - $160,000 a year
- Full-time
- 6 years
- Bachelor of Science
- Writing skills
- Health insurance
- 401(k)
Quick Apply
14d
FPGA Design/Verification Engineer
The Structures Company, LLC —Sunnyvale, CA
- $100 an hour
- Contract
- Mid-level
- Mentoring
- Scripting
- Health insurance
- Dental insurance
Quick Apply
3d
Secret Cleared FPGA Verification Engineer (Job ID 003150)
Innovien Solutions —Sunnyvale, CA
- From $80 an hour
- Full-time
- Analysis skills
- In-person
- Senior level
- Health savings account
- Health insurance
Quick Apply
13d
High speed Board Design Engineer
Pyramid Consulting, Inc —San Jose, CA
- $45 - $50 an hour
- Urgently hiring
- 7 years
- Analysis skills
- Mentoring
- Health insurance
- Dental insurance
Quick Apply
FPGA Engineer
Everforth —Sunnyvale, CA
- Full-time
- Maintenance
- Mid-level
- Master's degree
- Health insurance
- Dental insurance
Quick Apply
7d
Senior Electrical Engineer
Leoforce —San Jose, CA
- $186,000 - $225,000 a year
- 5 years
- Mentoring
- Linux
Quick Apply
6d
SoC ASIC Verification Engineer – New College Grad 2026
NVIDIA —Santa Clara, CA
- $100,000 - $189,750 a year
- Full-time
- Computer Science
- Master's degree
- Analysis skills
Hardware Verification Engineer, Entry Level
Synopsys —Sunnyvale, CA
- $90,000 - $136,000 a year
- Contract
- Computer science
- Computer Science
- Master's degree
3d
Jr. Product Test Engineer
Lewiz communications —San Jose, CA
- Linux
- Electrical Engineering
- Communication skills
SoC Verification Engineer – NoC / UVM
Advanced Micro Devices, Inc —San Jose, CA
- Hybrid work
- Master's degree
- Senior level
- Electrical Engineering
SoC Verification Lead
NVIDIA —Santa Clara, CA
- $232,000 - $368,000 a year
- Full-time
- 11+ years
- Master's degree
- Experience equivalent to degree accepted
Product Manager - Verification IP
Siemens —Fremont, CA
- $10 - $15 an hour
- Full-time
- Hybrid work
- 8 years
- Product management
- Senior level
FPGA Field Application Engineer
GOWIN Semiconductor Corp —San Jose, CA
- Email
- Computer science
- Computer Science
- Mid-level
Senior IP Verification Engineer
NVIDIA —Santa Clara, CA
- $136,000 - $264,500 a year
- Full-time
- Hybrid work
- 5 years
- Bachelor of Science
- Senior level
Verification Lead (Lead DV)
Lumilens —San Jose, CA
- Full-time
- Senior level
- Health insurance
- Dental insurance
11d
AI Inference Performance Engineer
NVIDIA —Santa Clara, CA
- $152,000 - $241,500 a year
- Full-time
- Computer science
- Computer Science
- 5 years

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Principal Applied Scientist, ML Codesign

Amazon.com Services LLC -
Sunnyvale, CA

Apply Now

Job Details

Full-time
$228,700 - $309,400 a year
13 days ago

Benefits

AD&D insurance
Health insurance
Dental insurance
Flexible spending account
RSU
Paid time off
Adoption assistance
Parental leave
Employee assistance program
Vision insurance
401(k) matching

Qualifications

Computer science
8 years
Senior level

Full Job Description

Define the joint optimization of model compression and silicon architecture for Amazon's next generation of edge and cloud inference accelerators. Your work will set the technical targets that propagate across the model, compiler, runtime, and silicon stack.

We are hiring a Principal Applied Scientist to be the technical leader who closes the loop between compression science and silicon design. Today's generation ships advanced quantization and large-model distillation in production, running multi-billion parameter language models at inference economics typical of much larger systems. Future generations target significantly larger models at the edge and in the cloud. You will be a principal architect of the next-generation accelerator and of the compression algorithms it executes natively. Few roles in the industry let one technical leader influence the model, the compiler, the runtime, and the silicon without organizational friction. This is one of them.

You have spent the last several years thinking about why hardware decisions and accuracy decisions live in different teams, and you want to be the person who owns both. You have published at MLSys, ISCA, MICRO, NeurIPS, or ICML on quantization, pruning, or hardware-aware training, and you want your next paper to ship in a chip rather than in a benchmark suite. You want a vertical stack—model, compression, compiler, runtime, operating system, silicon—where the same engineering organization owns every layer and a principal architect can move all of them.

Key job responsibilities

Define the hardware-aware compression roadmap for next-generation accelerators, working backward from accuracy targets on standard language and reasoning benchmarks including Massive Multitask Language Understanding (MMLU), GSM8K, HumanEval, and Instruction Following Evaluation (IFEval).

Own the joint optimization of compression algorithms (post-training quantization, quantization-aware training, knowledge distillation, structured pruning) with the underlying hardware.

Represent applied science in silicon architecture reviews and influence decisions across the memory and compute subsystems of the accelerator.

Set the science roadmap for the compression techniques the next architecture must support; validate that compression algorithms achieve target accuracy on the benchmarks our products are evaluated against.

Mentor a team of senior and mid-level applied scientists working on compression and hardware-aware training.

Serve as a single-threaded technical leader for the codesign agenda, accountable to senior leadership review.

About the team
Amazon's Devices and Services organization has shipped multiple generations of first-party silicon for consumer devices. The differentiating intellectual property across this portfolio is a custom machine learning processor co-designed with the compression algorithms it runs.

This role sits at the intersection of three teams. The Applied Science team produces compressed model checkpoints. The Silicon Engineering team designs the Application-Specific Integrated Circuits (ASICs). The Compiler and Runtime team lowers compressed models to silicon. You will be the principal architect who closes the loop across all three.

BASIC QUALIFICATIONS

Master's or PhD in Computer Science, Electrical Engineering, or a related field, or equivalent industry experience.

Eight or more years of industry experience with a track record of first-author or senior-author publications at top-tier venues in machine learning systems, computer architecture, or efficient machine learning.

Demonstrated experience defining or co-defining a hardware architecture that shipped, including silicon, Field Programmable Gate Array (FPGA), or large-scale software accelerator.

Deep expertise in at least two of the following: low-bit quantization, structured and unstructured pruning, knowledge distillation, sparse computation, hardware-aware neural architecture search.

Working knowledge of computer architecture fundamentals: memory hierarchy, dataflow architectures, on-chip interconnect.

PREFERRED QUALIFICATIONS

Direct experience contributing to silicon architecture for machine learning inference.

Published work demonstrating hardware-software codesign, where the compression algorithm and the hardware were optimized jointly rather than sequentially.

Experience applying compression techniques at large-model scale (tens of billions of parameters).

Familiarity with Application-Specific Integrated Circuit (ASIC) development flow, Register Transfer Level (RTL) review, or compiler intermediate representations including Multi-Level Intermediate Representation (MLIR) and OpenXLA.

Experience with Mixture-of-Experts (MoE) inference architectures.

Track record of mentoring senior applied scientists and shaping a multi-year research agenda.

Prior experience with vertically integrated stacks where the same team owns model, compiler, runtime, and silicon.

Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.

Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records.

Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.

The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits.

USA, CA, Sunnyvale - 228,700.00 - 309,400.00 USD annually

Apply Now

Refine Your Search

field programmable gate array jobs in milpitas, ca

Principal Applied Scientist, ML Codesign

Hardware Design Engineer

Senior Hardware Design Engineer – High Speed Boards

Labview Engineer

Design Verification Engineer

FPGA Design/Verification Engineer

Secret Cleared FPGA Verification Engineer (Job ID 003150)

High speed Board Design Engineer

FPGA Engineer

Senior Electrical Engineer

SoC ASIC Verification Engineer – New College Grad 2026

Hardware Verification Engineer, Entry Level

Jr. Product Test Engineer

SoC Verification Engineer – NoC / UVM

SoC Verification Lead

Product Manager - Verification IP

FPGA Field Application Engineer

Senior IP Verification Engineer

Verification Lead (Lead DV)

AI Inference Performance Engineer

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