Architecture & Hands-On Design
Define microarchitecture for complex digital blocks and subsystems
Actively contribute to RTL development for key components
Drive design tradeoffs across performance, power, area (PPA), and testability
RTL Development & Integration
Write, review, and integrate high-quality RTL
Lead block- and chip-level integration, resolving interface and system issues
Ensure designs are clean for lint, CDC/RDC, and synthesis
Back-End & Implementation Ownership
Ensure RTL is optimized for synthesis, timing, and physical design
Work on scan insertion, test architecture, and coverage closure
Perform, review and debug logic equivalence checking (LEC) results between RTL and netlists
Define and validate timing constraints (SDC) and complete timing closure
Drive and implement timing and functional ECOs as needed
Design Quality & Signoff
Drive signoff readiness including lint, CDC/RDC, synthesis, LEC, and timing checks
Ensure designs meet functional, timing, power, and test requirements
Support silicon bring-up, debug, and root-cause analysis
Cross-Functional Collaboration
Work closely with verification, physical design, DFT, and firmware teams
Align design decisions with verification plans and implementation
Constraints
Act as the technical bridge between front-end and back-end teams
Anticipated annual base salary for Member of Technical Staff: $200,000 - $250,000
