Requirements
MS plus 3 years or BS plus 6 years of minimum relevant experience or Ph.D in relevant fields.
Experience in at least one of below area is must:
- SerDes receiver circuit design, include CTLE, DFE, CDR, deserializer
- SerDes transmitter design, clock buffer distribution, TX driver, serializer
- SerDes clocking design, PLL,LCVCO, DLL, Phase interpolator, duty cycle correction circuit design
- Receiver adaptation, channel simulation, IBIS model, SERDES protocol such as PCIe/USB/SATA/Ethernet/PON(OLT,ONU)
Skills
- Hands-On Analog building block Design/layout & debug Experience
- Hands on experience in silicon test and debug
- Familiar with SerDes system operation
- Familiar with SerDes Architecture definition & System Modeling/analysis
- Familiar with SerDes protocols such as PCIe, USB, SATA, 802.3 Ethernet..etc
- Basic Knowledge on SerDes PCS/Controller design
- Basic Knowledge on hi-speed package, board design
- Familiar with both analog & mixed signal design flow & tools
- Familiar with Verilog, Verilog-A/AMS, Matlab
- Highly self-disciplined and motivated with strong integrity
