Principal ASIC Engineering Lead (Physical Design OR STA)
Up to $230k base, + 30% bonus plus around $800k-$1.2m in stocks which vests over 4 years.
Total first year realistic income $450-500k
Locations: San Jose, CA, Irvine, CA or Fort Collins, CO
Introduction
Are you a seasoned Engineer who excels at guiding complex semiconductor programs across areas such as physical design, STA, DFT, and packaging and a passion for working on bleeding-edge AI and high-performance silicon? Have you delivered enough chips to recognize hidden issues in EDA reports before they impact schedules, and can you clearly explain both the technical root cause and the long term solution? Do you enjoy deep technical discussions with engineering teams while also providing clear, high level summaries to management?
If this sounds like you, and you want to work on advanced compute and infrastructure silicon, this role may be an excellent match.
Top Reasons to Work With Us
Support customers building cutting edge ASICs in AI, HPC, networking, and storage
Collaborate with highly experienced cross functional engineering and technology teams
Influence the development of next generation semiconductor technologies
Take ownership of customer success from initial engagement through production
Shape design methodologies, best practices, and implementation strategies
Be part of a supportive, collaborative environment that values technical leadership
The Role / Responsibilities
As a senior technical leader, (NOTE: prior leadership experience NOT required) you will guide customer ASIC programs and ensure successful delivery of highly complex designs. (Approximately 80% hands on, 20% technical leadership).
Your responsibilities will include:
Leading end to end customer ASIC programs: RFQs, technology planning, IP integration, design, test, packaging, fabrication, bring up, and production
Advising customer teams on EDA best practices, design flows, and methodologies, including hosting Q&A sessions with technical experts
Identifying risks related to quality, schedule, or dependencies and coordinating mitigation plans with internal and external teams
Running physical design validation flows to ensure incoming customer netlists meet strict tape out quality requirements
Staying up to date on new technologies, IP developments, and application trends
Working closely with marketing, sales, legal, and compliance teams on program related discussions
Collaborating with and supporting other engineering teams as needed
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Essential Skills
Multiple tape outs at advanced process nodes
Ability to analyze PPA tradeoffs across library components, architectures, and implementation strategies
Strong understanding of low power design techniques and power management
Hands on experience in physical design or STA, along with EDA tools and flows covering physical design, logic simulation, test, and packaging
Programming or scripting experience
Excellent communication skills
Bonus Points For
Exposure to SERDES communication protocols
Experience in logic design, chip architecture, microarchitecture, Verilog RTL development, front end verification, DRC, and logic synthesis
Knowledge of DFT methods including scan, memory BIST, and repair
Benefits
Health, dental, and vision insurance
Life and disability insurance
FSA and HSA
401k with match
ESPP
Generous PTO
Annual bonus from 15-30% (depending on your level)
VERY generous stocks!
- For this position, you must be currently authorized to work in the United States without the need for sponsorship for a non-immigrant visa. This job was first posted by CyberCoders on 07/11/2026 and applications will be accepted on an ongoing basis until the position is filled or closed.Everforth CyberCoders is proud to be an Equal Opportunity Employer
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, age, sexual orientation, gender identity or expression, national origin, ancestry, citizenship, genetic information, registered domestic partner status, marital status, status as a crime victim, disability, protected veteran status, or any other characteristic protected by law. Our hiring process includes AI screening for keywords and minimum qualifications, and a virtual recruiter as part of the application process. A human recruiter reviews all results. Click here for details on our virtual recruiter . Everforth CyberCoders will consider qualified applicants with criminal histories in a manner consistent with the requirements of applicable state and local law, including but not limited to the Los Angeles County Fair Chance Ordinance, the San Francisco Fair Chance Ordinance, and the California Fair Chance Act. Everforth CyberCoders is committed to working with and providing reasonable accommodation to individuals with physical and mental disabilities. Individuals needing special assistance or an accommodation while seeking employment can contact a member of our Human Resources team at
[email protected] to make arrangements.
