At Micron-Boise, ID, we are undergoing a historic $15 billion investment in semiconductor manufacturing; construction began in early 2023, with DRAM production slated for the second half of the decade.
As a leader in the semiconductor industry, we build solutions that inspire and transform technology. With plans to invest more than $150 billion globally over the next decade in leading-edge manufacturing, we are looking for passionate people to join our Boise expansion team and contribute to the growth and innovation of the semiconductor industry.
This job requisition is to seek senior technical leaders in the field of process engineering to join ID1, reporting directly to Director of DE/WP/CMP. As a member of technical staff (MTS) or Senior member of technical staff (SMTS), you will play a pivotal role in driving innovation, leading technical projects, defining the technical roadmap, and mentoring fellow engineers. Your expertise will be instrumental in developing cutting-edge DRAM process solutions to support yield ramp-up. Your contribution will have a lasting impact on the DRAM industry!
Responsibilities for Process Engineering MTS/SMTS include (but not limited to):
Lead the development, characterization, and optimization of Dry Etch processes for advanced DRAM structures.
Collaborate cross-functionally with integration, metrology, equipment, and R&D teams to ensure process robustness and manufacturability.
Define and execute technical roadmaps aligned with DRAM scaling requirements and yield improvement goals.
Evaluate and implement new etch technologies, chemistries, and hardware platforms.
Mentor and guide developing engineers; foster a culture of innovation and technical excellence.
Collaborate with equipment vendors and external partners to co-develop solutions.
Drive root cause analysis and continuous improvement initiatives for process-related issues.
Present findings and recommendations to executive leadership and global teams.
Required Qualifications:
Ph.D. or Master’s degree in Electrical Engineering, Materials Science, Chemical Engineering, Physics, or related field.
Minimum 10 years of hands-on experience in Dry Etch process development, preferably in DRAM or advanced memory technologies.
Proven track record of technical leadership in semiconductor process engineering.
Deep understanding of plasma etch mechanisms, process control, and defect mitigation.
Experience with advanced etch tools (e.g., Lam, TEL, AMAT) and process characterization techniques.
Strong analytical, problem-solving, and communication skills.
Ability to lead cross-functional teams and manage complex projects.
Preferred Skills:
Experience with high aspect ratio etching, critical dimension control, and selectivity challenges in DRAM.
Familiarity with data analytics, DOE methodologies, and SPC tools.
Knowledge of integration challenges in sub-20nm DRAM nodes.
