Title: ASIC RTL Design Engineer
Hybrid Role- 3 days onsite/2 days remote- (Burlingame, CA or Burlington, MA)
Length of Contract: 6-9 months - Temp-to-Perm
Ideal Start Date: 6/1/2026 or later (Sooner the better)
Hours: 40 hours per week
Client is looking for an ASIC RTL designer to Own end-to-end design of complex SoC CPU subsystems, advanced nodes (28nm), driving architecture, RTL implementation, and tapeout. Focus on high-performance datapaths, PPA optimization, and cross-functional integration across silicon, firmware, and system teams.
- -8–12+ years in Hands-on ASIC/SoC RTL design for CPU Subsystems (MMUs and non-MMUs)
- Familiarity or ideally prior experience with, UPF design flow for power management
- Strong SystemVerilog/Verilog RTL development (datapaths, control logic, state machines)
- Proven experience owning subsystems from architecture → RTL → tapeout
- Deep understanding of PPA tradeoffs, timing closure, clock/reset, and power-aware design (Will need to have overlap with STA Portion of the Design life cycle - Deep collaboration with backend)
- Experience designing high throughput datapaths (buffering, arbitration, memory hierarchy)
- Experience with compute-intensive pipelines (DSP, AI, beamforming, MAC datapaths)
- Exposure to sensor / imaging systems (e.g., ultrasound, data acquisition)
- Experience with programmable compute blocks (AI accelerators, MPUs, eFPGA)
- Background in advanced nodes (≤28nm) and cross-functional collaboration (verification, systems, firmware)
Pay: $83.00 - $93.00 per hour
Benefits:
- 401(k)
- Dental insurance
- Health insurance
- Life insurance
- Vision insurance
Work Location: In person
