Title: Sr. SRAM Layout Design Engineer
Duration: Fulltime/Contract Both
Location: Santa Clara, CA (Onsite)
May Consider OPT EAD with 4+yrs of relevant exp for Contracting
What you will be doing:
- Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies.
- Develop and improve floorplans for SRAM and memory blocks, covering array layout, periphery positioning, power grid design, routing channels, and macro assembly.
- Carry out, debug, and complete DRC, LVS, ERC, antenna, and associated physical verification checks with tools such as Calibre, ICV, or similar workflows.
- Support EM/IR review, power integrity, density/fill, DFM, dummy insertion, layout-dependent effects, and other requirements for tapeout.
- Collaborate with circuit designers to convert schematics into layouts, ensuring matching, symmetry, shielding, parasitic targets, and reliability constraints are maintained.
- Collaborate with PnR and integration teams to resolve top-level DRC/LVS, pin access, boundary, routing, power-grid, and macro-integration issues.
- Implement and advance layout methodology, checklists, reusable practices, and quality standards for consistent memory IP delivery.
- Collaborate with foundry, CAD, and methodology teams on rule interpretation, deck behavior, waivers, and advanced-node process constraints.
- Review layouts, mentor junior engineers, and help raise layout quality and execution rigor across the team.
What we need to see:
- Have a BSEE or equivalent experience
- 10+ years of custom IC layout experience, including 5+ years in SRAM, memory compiler, or full-custom memory IP layout.
- Hands-on participation in advanced CMOS technology initiatives, preferably concentrating on FinFET or GAA nodes at 5nm, 3nm, or smaller dimensions.
- Solid grasp of SRAM and memory layout principles.
- Extensive experience in Cadence Virtuoso applied to custom layout creation and assessment.
- Extensive experience in DRC/LVS debugging using Calibre, ICV, or similar physical verification tools.
- Experience with floor planning, block-level routing, macro assembly, pin planning, boundary/interface management, and top-level physical verification.
- Direct familiarity with advanced-node layout limitations and layout-dependent phenomena, including LOD, density/fill, matching, symmetry, shielding, electromigration, IR drop, and DFM or similar expertise.
- Ability to work effectively with circuit build, physical build, integration, CAD, and foundry teams.
- Clear communication, strong ownership, good judgment, and the ability to mentor other engineers.
- Knowledge of layout automation or AI tools is a definite plus.
Thanks & Regards
Aniruddh Ranjan
Senior Technical Recruiter
Contact: 1408 443 3660 | +91-770-382-0817 | [email protected]
Pay: Up to $100,000.00 per year
Benefits:
- 401(k) matching
- Dental insurance
- Paid time off
Application Question(s):
- What are you comfortable with: Contract/Fulltime ?
Experience:
- Layout design: 5 years (Required)
- CMOS technology (FinFET or GAA): 3 years (Required)
- DRC/LVS debugging using Calibre/ICV: 4 years (Required)
Ability to Commute:
- Santa Clara, CA 95051 (Required)
Ability to Relocate:
- Santa Clara, CA 95051: Relocate before starting work (Required)
Work Location: In person
