Principal RTL Design Engineer - PCIe / CXL / High-Speed SoC
Job Title: Principal RTL Design Engineer - PCIe / CXL / High-Speed SoC
Location: Santa Clara, CA
Compensation: $200K - $250K base DOE plus bonus and RSUs ($300K - $350K+ total comp.)
Requirements: RTL Design, Verilog / SystemVerilog, PCIe / CXL / Ethernet / UALink, High-Speed SoC Design
Position Overview
As a Sr. Staff or Principal RTL Design Engineer, you will join the Connectivity Business Unit within the Data Center Group (DCG), contributing to the development of advanced silicon solutions for next-generation data center infrastructure. In this role, you will be instrumental in driving the design and delivery of high-performance ASICs that power industry-leading products for hyperscale and enterprise customers. This position offers the opportunity to work alongside world-class engineers, influence key design methodologies, and contribute to cutting-edge technologies in an environment that values innovation, collaboration, and execution excellence.
Key Responsibilities
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Own and implement RTL design blocks, demonstrating strong RTL coding expertise.
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Collaborate with the architecture team to understand and define feature enhancements.
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Translate specifications into efficient RTL implementations.
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Ensure all design quality standards and criteria are consistently met.
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Partner with physical design teams to review timing reports, perform STA, write SDC constraints, analyze power, and provide guidance on floorplanning and timing closure.
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Work closely with the verification team on pre-silicon activities, including test plan reviews, coverage analysis, simulations (block and full-chip), performance evaluation, and debugging; strong debug skills are essential.
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Define subsystem microarchitecture and register specifications for complex SoCs, and contribute to specification development.
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Lead and participate in detailed reviews of performance, architecture, and design requirements with cross-functional teams, IP vendors, and customers.
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Contribute to the development and evaluation of design and verification methodologies, and help enhance existing processes.
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Collaborate with post-silicon and software and firmware teams to support silicon bring-up and performance optimization.
Qualifications
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Bachelor's degree in Electrical Engineering or a related field with 15+ years of relevant experience, or a Master's/PhD with 12+ years of experience.
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Strong proficiency in Verilog/SystemVerilog RTL development, including SystemVerilog assertions.
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Experience working on complex subsystems, IPs, or switch SoCs involving PCIe, CXL, Ethernet, or UALink.
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Deep knowledge of PCIe, CXL, Ethernet, or UALink protocols.
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Expertise in microarchitecture development and translating requirements into robust designs.
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Proven ability to collaborate effectively with third-party IP vendors and customers.
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Extensive experience in RTL design, synthesis, constraint development, static timing analysis, debugging, block-level functional verification, logical equivalence checking, and CDC/RDC.
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Solid experience with implementation and timing closure for high-speed designs.
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Hands-on experience across the full chip development lifecycle, with strong proficiency in front-end and mid-end design tools and methodologies.
Benefits
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Comprehensive medical, dental, and vision plans
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Life insurance and disability plan options
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401(k)
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RSUs
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ESPP
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Paid company-selected holidays & floating holidays
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PTO - generous time off programs
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Career growth opportunities
- For this position, you must be currently authorized to work in the United States without the need for sponsorship for a non-immigrant visa. CyberCoders will consider for Employment in the City of Los Angeles qualified Applicants with Criminal Histories in a manner consistent with the requirements of the Los Angeles Fair Chance Initiative for Hiring (Ban the Box) Ordinance.This job was first posted by CyberCoders on 07/15/2026 and applications will be accepted on an ongoing basis until the position is filled or closed.Everforth CyberCoders is proud to be an Equal Opportunity Employer
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, age, sexual orientation, gender identity or expression, national origin, ancestry, citizenship, genetic information, registered domestic partner status, marital status, status as a crime victim, disability, protected veteran status, or any other characteristic protected by law. Our hiring process includes AI screening for keywords and minimum qualifications, and a virtual recruiter as part of the application process. A human recruiter reviews all results. Click here for details on our virtual recruiter . Everforth CyberCoders will consider qualified applicants with criminal histories in a manner consistent with the requirements of applicable state and local law, including but not limited to the Los Angeles County Fair Chance Ordinance, the San Francisco Fair Chance Ordinance, and the California Fair Chance Act. Everforth CyberCoders is committed to working with and providing reasonable accommodation to individuals with physical and mental disabilities. Individuals needing special assistance or an accommodation while seeking employment can contact a member of our Human Resources team at
[email protected] to make arrangements.
