King, Washington
Job Summary
The Technical Program Manager (TPM) – Advanced SoC Physical Design is responsible for leading end-to-end execution of complex SoC implementation programs from RTL handoff through GDSII signoff. The role combines deep technical expertise in advanced-node Physical Design with strong program leadership, customer engagement, risk management, and cross-functional coordination across Design, Verification, DFT, Package, CAD, and Silicon Validation teams.
The TPM serves as the single point of accountability for delivery predictability, schedule adherence, quality, customer communication, and successful tape-out execution. The ideal candidate possesses strong full-chip implementation experience across advanced process technologies and has demonstrated success driving large-scale ASIC/SoC programs to production.
Key Responsibilities
Program & Delivery Ownership
Own end-to-end delivery of full-chip SoC Physical Design and implementation programs.
Define execution plans, milestones, resource strategy, dependencies, and tape-out schedules.
Drive predictable delivery across RTL-to-GDSII implementation activities.
Manage program risks, dependencies, escalations, and mitigation plans.
Ensure adherence to schedule, quality, cost, and customer commitments.
Lead program reviews, status reporting, MBR/QBR discussions, and executive communication.
Technical Leadership
Provide technical oversight across:
Design Planning & Floorplanning
Power Planning / PDN
Synthesis
Place & Route
Clock Tree Synthesis (CTS)
Timing Closure
Signal Integrity
Power Optimization
Physical Verification
EM/IR Analysis
Signoff & Tape-out
Drive PPA (Performance, Power, Area) optimization strategies.
Guide teams on advanced-node implementation challenges and methodologies.
Review implementation quality, technical risks, and closure readiness
Full-Chip Integration & Cross-Functional Collaboration
Coordinate execution across RTL Design, Verification, Physical Design, DFT, Package, CAD, Library, IP, and Foundry teams.
Drive alignment on design handoffs, integration milestones, and signoff criteria.
Resolve technical and schedule conflicts impacting tape-out readiness.
Ensure smooth execution of RTL-to-GDSII flow across multiple stakeholders
Customer Engagement
Act as primary customer-facing technical and program interface.
Drive scope clarification, estimation reviews, milestone alignment, and delivery commitments.
Lead customer reviews and executive updates.
Proactively manage customer expectations and escalations
Team Leadership & Capability Development
Build and lead high-performing implementation teams.
Mentor technical leads and program engineers.
Assess team capabilities, identify skill gaps, and develop succession plans.
Support staffing, onboarding, resource forecasting, and utilization planning
Governance & Operational Excellence
Establish execution dashboards, metrics, and KPIs.
Drive continuous improvement, automation, and methodology enhancements.
Champion AI/ML and EDA productivity solutions where applicable.
Ensure compliance with organizational and customer processes
Skill Requirements
Physical Design Expertise
Strong full-chip SoC implementation experience from RTL-to-GDSII.
Expertise in:
Floorplanning
Power Planning
Synthesis
P&R
CTS
Timing Closure
Physical Verification
EM/IR Signoff
ECO Management
Deep understanding of advanced-node design challenges (5nm/3nm and below preferred).
EDA Tools
Strong exposure to Synopsys and/or Cadence implementation flows.
Familiarity with:
ICC2
Fusion Compiler
Innovus
Tempus
PrimeTime
RedHawk
Calibre
Voltus
StarRC
SoC Architecture Knowledge
Understanding of:
CPU/GPU based architectures
High-speed interfaces
Memory subsystems
NoC/Fabric architectures
Low-power design methodologies
Multi-voltage and power-domain implementations
Program Management
Experience managing large global engineering teams.
Strong project planning, budgeting, forecasting, and risk management skills.
Expertise in stakeholder communication and executive reporting
Other Requirements
Experience & Qualifications
Required
B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, Computer Engineering, or related field.
12–18+ years of semiconductor industry experience.
Minimum 5+ years leading SoC implementation programs or full-chip tape-outs.
Proven experience managing customer-facing engagements and large delivery teams.
Track record of successful silicon tape-outs at advanced process nodes.
Preferred
Experience managing multi-site/global development teams.
Exposure to HPC, AI/ML, Data Center, Networking, Mobile, or Automotive SoCs.
PMP, PgMP, Agile, or equivalent program management certification.
Experience with AI-assisted design methodologies and EDA automation
Maximum Salary (US): 192000
Minimum Salary (US): 95000
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