Principal Signal Integrity & Hardware Systems Engineer (PCIe Gen
Job Title: Principal Signal Integrity & Hardware Systems Engineer (PCIe Gen5/6)
Location: Santa Clara, CA
Compensation: $150K - $250K base DOE plus bonus and RSUs
Requirements: Signal Integrity, PCIe (Gen5/6), High-Speed SerDes, PCB Design, Power Integrity (PI) Analysis, Sigrity / Ansys HFSS, Reference Board Design, EM Modeling & Simulation
Position Overview
We are seeking an experienced Principal Signal Integrity & Hardware Systems Engineer to lead design and verification of high-performance digital hardware with a focus on PCIe Gen5/Gen6 and 25Gbps+ SerDes interfaces. The role combines advanced signal and power integrity analysis, reference board and PCB design guidance, EM/field simulation, and hands-on lab validation to ensure robust system-level performance. You will drive architecture decisions, mentor engineers, and collaborate across cross-functional teams to deliver scalable, manufacturable solutions for next-generation products.
Key Responsibilities
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Lead signal integrity (SI) and hardware systems engineering efforts for PCIe Gen5/Gen6 and other high-speed SerDes interfaces, driving architecture choices, budgeting, and tradeoffs.
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Own reference board and PCB design best practices: define stackups, routing topologies, connector/cable interfaces, and layout constraints for high-speed channels.
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Perform detailed SI and PI analysis using tools such as Cadence Sigrity, SIsoft, Ansys HFSS, and other EM solvers to model channel loss, crosstalk, reflections, and package effects.
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Develop and run channel and link-level simulations (IBIS-AMI, eye, BER, jitter/power-aware analyses) to validate compliance with PCIe and other protocol margins.
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Lead power integrity (PI) analysis and decoupling strategies to minimize supply noise impact on SerDes and system timing.
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Create EM models of packages, connectors, and PCBs, and use them to inform design changes to improve signal fidelity and EMC performance.
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Plan and execute lab validation: setup and run TDR/TDT, VNA, high-speed oscilloscope, BERT, and related measurements for debug and release verification.
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Collaborate closely with board layout teams, package engineers, firmware, system architects, and manufacturing to resolve signal and hardware issues from pre-silicon through production.
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Mentor and coach other engineers, establish SI/PI processes and checklists, and drive knowledge sharing across the organization.
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Support supplier and partner engagements, including reviewing third-party PCB stackups, evaluating test fixtures, and providing technical direction for prototypes and NPI runs.
Qualifications
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Bachelors or Masters degree in Electrical Engineering or related field; PhD preferred but not required.
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5+ years of hands-on experience in signal integrity, hardware systems, and high-speed digital design with demonstrated leadership on complex products.
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Proven experience designing and validating PCIe Gen5 and/or Gen6 links and related SerDes interfaces (protocol compliance and link margining).
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Strong PCB and reference board design background, including stackup definition, controlled impedance routing, and connector/cable integration.
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Proficiency with SI/PI and EM tools such as Cadence Sigrity, SiSoft, Ansys HFSS, Keysight ADS, or similar simulation suites.
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Expertise in IBIS-AMI modeling, channel simulation, BER/eye analysis, and jitter decomposition techniques.
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Experience with power integrity analysis and decoupling strategies for high-speed digital systems.
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Hands-on lab experience with high-speed test equipment (oscilloscopes, VNAs, TDRs, BERTs) and troubleshooting methodologies.
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Experience with EM/package modeling, signal/power co-simulation, and thermal/EM-aware system trade-offs.
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Strong scripting and data-analysis skills (Python, MATLAB, or similar) to automate simulations and post-process results.
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Excellent communication and cross-functional collaboration skills; experience mentoring engineers and defining engineering processes.
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Ability to manage multiple projects, prioritize technical risks, and deliver to schedule in a fast-paced environment.
Benefits
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Comprehensive medical, dental, and vision plans
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Life insurance and disability plan options
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401(k)
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RSUs
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ESPP
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Paid company-selected holidays & floating holidays
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PTO - generous time off programs
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Career growth opportunities
- For this position, you must be currently authorized to work in the United States without the need for sponsorship for a non-immigrant visa. CyberCoders will consider for Employment in the City of Los Angeles qualified Applicants with Criminal Histories in a manner consistent with the requirements of the Los Angeles Fair Chance Initiative for Hiring (Ban the Box) Ordinance.This job was first posted by CyberCoders on 06/04/2026 and applications will be accepted on an ongoing basis until the position is filled or closed.Everforth CyberCoders is proud to be an Equal Opportunity Employer
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, age, sexual orientation, gender identity or expression, national origin, ancestry, citizenship, genetic information, registered domestic partner status, marital status, status as a crime victim, disability, protected veteran status, or any other characteristic protected by law. Our hiring process includes AI screening for keywords and minimum qualifications, and a virtual recruiter as part of the application process. A human recruiter reviews all results. Click here for details on our virtual recruiter . Everforth CyberCoders will consider qualified applicants with criminal histories in a manner consistent with the requirements of applicable state and local law, including but not limited to the Los Angeles County Fair Chance Ordinance, the San Francisco Fair Chance Ordinance, and the California Fair Chance Act. Everforth CyberCoders is committed to working with and providing reasonable accommodation to individuals with physical and mental disabilities. Individuals needing special assistance or an accommodation while seeking employment can contact a member of our Human Resources team at
[email protected] to make arrangements.
