Waymo is an autonomous driving technology company with the mission to be the world's most trusted driver. Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the Waymo Driver—The World's Most Experienced Driver™—to improve access to mobility while saving thousands of lives now lost to traffic crashes. The Waymo Driver powers Waymo's fully autonomous ride-hail service and can also be applied to a range of vehicle platforms and product use cases. The Waymo Driver has provided over ten million rider-only trips, enabled by its experience autonomously driving over 100 million miles on public roads and tens of billions in simulation across 15+ U.S. states.
Waymo's Compute Team is tasked with a critical and exciting mission: We deliver the compute platform responsible for running the fully autonomous vehicle's software stack. To achieve our mission, we architect and create high-performance custom silicon; we develop system-level compute architectures that push the boundaries of performance, power, and latency; and we collaborate closely with many other teammates to ensure we design and optimize hardware and software for maximum performance. We are a multidisciplinary team seeking curious and talented teammates to work on one of the world's highest performance automotive compute platforms.
This role follows a hybrid work schedule and you will report to a Silicon Engineering Lead
You will:
- Partner with design and architecture teams to translate hardware specifications into comprehensive, scalable verification plans
- Drive the development of testbenches, reference models, and stimulus to validate mission-critical functionality and performance
- Architect and enhance verification environments, contributing to shared tools and reusable methodologies across the organization
- Evaluate, integrate, and verify third-party Verification IP (VIP) to accelerate the development cycle
- Define and analyze coverage metrics (functional and code) to ensure design readiness and closure
- Advocate and establish verification best-practices
You have:
- 3+ years of experience building and maintaining complex testbenches using UVM/SystemVerilog
- Proven track record with constrained-random generation, functional coverage, and SVA (SystemVerilog Assertions)
- Deep understanding of complex digital logic and the ability to debug intricate hardware/software interactions
- Proficiency in Python for developing scalable automation frameworks, data analysis tools, and regression management suites
- Excellent verbal and written communication skills, ability to collaborate with cross-functional teams
- Strong analytical skills in root-causing failures across RTL, testbench, and environment layers
We prefer:
- Experience spanning initial specification through post-silicon bring-up and validation
- Familiarity with power-aware verification (UPF), formal verification, or hardware-software co-validation
- Domain expertise in ML accelerators, high-speed interconnects (NoCs), or high-bandwidth memory
- Experience with C/C++ for reference model development and enhancement
- Hands-on experience with industry-standard interfaces such as PCIe Gen 5/6, DDR5, or Ethernet
- Interest or experience in leveraging Generative AI and LLMs to accelerate verification workflows, such as automated testbench generation, documentation, or failure log analysis
