Santa Clara, California
Job Summary
We are seeking an Emulation Build Engineer to own the end-to-end process of building, compiling, and validating RTL design models targeting hardware emulation and prototyping platforms — specifically Cadence Palladium , Cadence Protium , and/or Synopsys ZeBu . You will be the critical bridge between RTL design teams and validation/software teams, ensuring that high-quality, synthesizable emulation models are delivered on schedule to enable early firmware development, hardware-software co-verification, and system-level validation.
Key Responsibilities
Emulation Model Build & Compilation
Build, compile, and optimize RTL-to-gate/behavioral models targeting Palladium, Protium, and/or ZeBu emulation platforms
Own the emulation build flow from RTL ingestion through synthesis, partitioning, mapping, place-and-route, and bitstream/image generation
Resolve synthesis and compilation errors including unresolved modules, black-box instantiation, clock/reset inference, memory mapping , and multi-driver conflicts
Implement and maintain RTL waivers, workarounds, and design abstraction (memory wrappers, analog stubs, IP replacements) to achieve clean compilations
Optimize build configurations for compile time, resource utilization, emulation speed (MHz), and capacity across target platforms
Manage incremental and hierarchical build strategies to reduce turnaround time for design iterations
Support multi-domain and multi-clock designs with proper clock modeling and domain crossing handling
Model Validation & Quality
Validate emulation models through sanity tests, boot tests, and golden-reference comparisons against RTL simulation
Ensure functional equivalence between RTL simulation and emulation by running correlation test suites
Debug and resolve model mismatches (simulation vs. emulation) due to synthesis artifacts, X-state handling, timing differences, or initialization issues
Validate memory models, I/O interfaces, and transactor/synthesizable BFM integration
Perform coverage analysis on emulation models and track model quality metrics
Maintain a regression suite for build-level validation (smoke tests, connectivity checks)
Infrastructure & Automation
Develop and maintain automated build pipelines (CI/CD) for nightly/weekly emulation model builds
Create scripts and tools for build monitoring, error triage, capacity tracking , and build status reporting
Maintain version-controlled build configurations , design collateral, and release notes
Manage compute farm resources (LSF/SGE/Slurm) and optimize job scheduling for emulation builds
Track and manage platform licenses and capacity allocation across projects
Develop dashboards and metrics for build health, turnaround time, and platform utilization
Collaboration & Support
Partner with RTL design teams on design readiness, coding guidelines, and synthesizability best practices for emulation
Work with verification/validation teams to integrate transactors, probes, and debug infrastructure into emulation models
Collaborate with firmware/software teams to deliver validated models for early SW development and hardware-software co-validation
Coordinate with EDA vendor support (Cadence, Synopsys) for tool issues, feature requests, and platform upgrades
Support silicon bring-up teams with emulation-correlated debug and pre-silicon regression data
Participate in project planning to communicate build schedules, risks, and dependencies
Skill Requirements
Education: B.S./M.S. in Electrical Engineering, Computer Engineering, or related field Experience: 3–8+ years in emulation model build, FPGA prototyping, or related hardware compilation roles Hands-on experience with one or more emulation/prototyping platforms: Platform Key Skills Cadence Palladium xeCompiler, xeDesignOptimizer, multi-domain
Strong understanding of RTL design constructs and synthesizability rules (Verilog/SystemVerilog)
Experience with logic synthesis concepts (technology mapping, optimization, timing constraints)
Proficiency in scripting and automation : Python, Perl, Tcl, Bash, Makefiles
Knowledge of memory modeling (SRAM, ROM, FIFO wrappers) and abstraction for emulation
Familiarity with clock modeling strategies (clock generators, clock muxes, PLLs) in emulation
Understanding of design hierarchy, IP integration , and SoC-level build complexity
Experience with version control (Git, Perforce) and build management systems
Other Requirements
Platform
Key Skills
Cadence Palladium
xeCompiler, xeDesignOptimizer, multi-domain clocking, ICE/SCE modes, speed optimization
Cadence Protium
FPGA-based prototyping, partitioning, multi-FPGA mapping, pin multiplexing, timing closure
Synopsys ZeBu
zFAST/zTOP compile, design partitioning, ZCUI, transactor integration, ZeBu Server
Maximum Salary (US): 148000
Minimum Salary (US): 78000
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