San Jose, California
Job Summary
We are seeking a highly skilled and innovative **Advanced Packaging Design Engineer** specializing in Silicon Interposer and Redistribution Layer (RDL) technologies. In this role, you will drive the physical design, layout, and implementation of next-generation 2.5D and 3D heterogeneous packaging architectures. You will collaborate closely with ASIC architecture, foundry partners, OSATs, and Signal/Power Integrity (SI/PI) teams to deliver robust, high-density interconnect solutions for high-performance computing (HPC), AI accelerators, and high-speed networking applications.
Key Responsibilities
### 1. Physical Layout & Routing * **Advanced Interposer Design: ** Own the end-to-end physical design, floorplanning, and layout of passive/active silicon interposers and high-density RDL fan-out packages. * **High-Density Interconnects: ** Execute complex routing for ultra-fine-pitch microbumps, C4 bumps, TSVs (Through-Silicon Vias), microvias, and pillar structures. * **Interface Implementations: ** Route critical high-speed, high-bandwidth interfaces such as **HBM (High Bandwidth Memory)**, **PCIe Gen 5/Gen 6**, and ultra-short-reach (USR/XSR) die-to-die interfaces with stringent impedance controls. ### 2. Co-Design & Optimization * **Chiplet Integration: ** Actively drive die-package-board co-optimization (DPCO) by mapping bump assignments and floorplans acro
Skill Requirements
1. Advanced Proficiency In Allegro Pcb For Pcb Layout And Design.
2. Strong Knowledge Of Cad Software For 2D And 3D Design Applications.
3. In-Depth Understanding Of Design Principles And Methodologies.
4. Excellent Leadership And Team Management Skills.
5. Strong Communication And Presentation Abilities To Effectively Convey Design Concepts.
Other Requirements
### Soft Skills & Experience
- Excellent cross-functional communication skills, with a proven ability to bridge gaps between silicon design teams and manufacturing foundries.
- Strong debugging and problem-solving skills when addressing complex DRC violations and multi-die routing bottlenecks.
## Education & Experience Requirements
- **Education: ** Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Electronics, Microelectronics, Materials Science, or a closely related field.
- **Experience: ** * **Engineer: ** 3+ years of experience in silicon physical design or IC package layout.
- **Senior/Staff Engineer: ** 6–10+ years of hands-on experience delivering production-ready 2.5D/3D interposer or high-density fan-out (HDFO) designs from concept to tape-out.
Maximum Salary (US): 148000
Minimum Salary (US): 78000
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