In this role, you will lead and manage a high-caliber team within Rivian’s Perception organization. You are responsible for the end-to-end strategy of how our most advanced neural networks are compressed, optimized, and deployed onto Rivian’s custom embedded compute platforms. You will bridge the gap between high-level ML research and low-level silicon and hardware constraints, ensuring that Rivian’s autonomy stack remains "performance-first" while scaling to meet next-generation safety requirements.
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Hardware-Software Co-Design Leadership: Characterize perception and planner model bottlenecks on RAP silicon, communicate optimization requirements, and contribute hardware architecture specifications for accelerator subsystems to jointly drive deployment solutions targeting future RAP generations. Propose novel accelerator architectures and neural network engine enhancements where workload analysis reveals fundamental limitations in current silicon.
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Team Leadership & Mentorship: Build, lead, and develop a world-class team of hardware-software machine learning acceleration engineers spanning performance modeling, systems optimization. and software integration. Manage performance, set technical goals, drive hiring strategy, and foster a culture of high-performance hardware-software co-design and model optimization engineering.
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Power/Performance Modeling Oversight: Establish and oversee the team's cycle-accurate and analytical performance/power modeling capability for evaluating RAP-family accelerator design tradeoffs (compute throughput, memory bandwidth, INT8/sparse utilization efficiency). Ensure modeling outputs directly inform silicon design decisions for future tape-outs.
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Acceleration Roadmap & Strategy: Define and own the 2 to 3 year hardware-aware acceleration strategy spanning model compression (Pruning, Quantization, NAS), runtime optimization, and collaborate on co-design of custom hardware accelerator features (ISA extensions, fixed-function units, scheduling primitives) with Rivian's silicon team targeting RAP2 and future ACM generations.
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Cross-Functional Delivery & Tech Transfer: Partner with Perception, Planning, Silicon Architecture, and Embedded Systems leadership to ensure that research models can run in real-time on ACM3 and future autonomy compute modules without compromising safety, thermal envelope, or latency targets. Drive tech transfer of validated acceleration techniques into hardware architecture requirements for future RAP generations.
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Patents & Research Dissemination: Build a culture of intellectual property creation and external visibility. Drive patent disclosures for novel hardware-software co-design architectures and model acceleration techniques related to Rivian's custom silicon roadmap. Ensure the team communicates research progress and results via internal and external symposiums and publications.
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Education: MS or Ph.D. in CS, EE, or related field with 10+ years of industrial
experience, including 2+ years in a technical leadership or management capacity. -
System Mastery: Expert-level knowledge of the ML stack: from High-level Frameworks
(PyTorch) to IR/Compilers (MLIR, TVM, XLA) to Silicon (GPU/NPU/DSP). -
Optimization Specialist: Proven track record of deploying large-scale models into
production via Quantization-Aware Training (QAT), FP8/INT4 precision, and Neural
Architecture Search (NAS). -
Architectural Fluency: Ability to read hardware spec sheets (data sheets, ISA) and
translate "Peak TFLOPS" into realistic "Application Throughput." -
Architectural Innovation: Ability to convert ideas into silicon.
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Low-Level Coding: Proficient in C++, CUDA, and assembly-level optimization, with
the ability to perform deep-dive code reviews on custom kernels. -
0th and 1st Order Thinking: Deep understanding of the "Elephant in the room":
optimizing non-differentiable planning objectives and managing the trade-offs between
open-loop and closed-loop simulation efficiency. -
Profiling Expert: Mastery of system-wide profiling tools (NVIDIA Nsight, PyTorch
Profiler, VTune) to identify bottlenecks across the CPU-GPU-NPU interconnects.
