We are seeking a passionate Optical Engineer to join our research and development team. This role focuses on delivering state-of-the-art near-to-eye display system technologies. The ideal candidate will have expertise in novel integrated photonics device design and metrology, gained through a Ph.D. or industry experience.
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Design and develop complete Photonic Integrated Circuits (PICs), from fundamental component blocks to full-circuit implementations, with a strong emphasis on active device integration.
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Generate, verify, and prepare fabrication-ready layout files, ensuring compliance with foundry Process Design Kits (PDKs) for external fabrication.
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Conduct systematic design analysis, including optimization and parametric studies, to guide design decisions.
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Support the entire design-to-fabrication pipeline, from initial concept through tapeout, coordinating closely with cross-functional teams and external partners.
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Collaborate with program leadership, Technical Program Managers (TPMs), and researchers on PIC designs that align with overall program objectives.
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MS or Ph.D. degree in Electrical Engineering, Optical Sciences, Physics, or a closely related field.
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3+ years of hands-on experience in the design, simulation, and layout of PICs for visible or IR wavelengths on platforms such as Si, SiN, LiNbO, or BTO.
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3+ years of experience utilizing photonic device simulation and electromagnetic modeling tools for both component and circuit-level analysis (e.g., Lumerical FDTD/MODE/DEVICE, Ansys Photonics, Synopsys RSoft, or COMSOL Multiphysics).
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2+ years of experience with PIC layout tools and GDSII generation (e.g., KLayout, Cadence Virtuoso, gdsfactory, or equivalent), including familiarity with foundry PDK integration and design rule verification.
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2+ years of experience with scientific programming (e.g., Python or MATLAB) for scripting, design automation, and analysis.
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1+ years of experience supporting or executing PIC tapeouts at a commercial semiconductor foundry, including an understanding of fabrication process constraints (e.g., propagation losses, sidewall roughness, etch non-idealities).
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3+ years experience in active PIC design, fabrication, and validation, particularly for visible wavelengths on LiNbO or BTO platforms.
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3+ years of experience in design space exploration, sensitivity analysis, and statistical performance/yield modeling for photonic circuits.
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3+ years of experience with one or more major photonic simulation tool suites (e.g., Lumerical, Synopsys, COMSOL, or equivalent).
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2+ years of experience utilizing photonic circuit-level simulation tools (e.g., Lumerical Interconnect, Synopsys OptSim, or VPIphotonics) for system-level performance evaluation.
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2+ years of experience in photonic device characterization and test, including both optical and electro-optic measurements.
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1+ years experience with fiber optics, free-space optics, PIC packaging, and comprehensive device characterization.
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1+ years experience with semiconductor fabrication processes and a deep understanding of process-induced performance limitations, such as optical losses, sidewall roughness, and process variability.
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Demonstrated ability to directly incorporate fabrication constraints into PIC designs (e.g., optimizing minimum feature sizes and bend radii, implementing effective tapering strategies, and using layout techniques to mitigate scattering and coupling losses).
5-7 years
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PIC Design & Simulation: 3+ years designing, simulating, and laying out photonic integrated circuits (PICs) for visible/IR wavelengths.
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Photonic Modeling Tools: Proficiency with tools like Lumerical, Ansys Photonics, Synopsys RSoft, or COMSOL for device/circuit analysis.
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PIC Layout & Tapeout: Experience with layout tools (KLayout, Cadence Virtuoso, gdsfactory), GDSII generation, and supporting tapeouts at commercial foundries.
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Active PIC Design & Validation: Experience in active PIC design, fabrication, and validation, especially for visible wavelengths.
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Device Characterization: Skills in optical/electro-optic measurements, fiber optics, free-space optics, and PIC packaging.
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Statistical Modeling & Sensitivity Analysis: Experience in design space exploration, yield modeling, and incorporating fabrication constraints.
Job Type & Location
This is a Contract position based out of Redmond, WA.
Pay and Benefits
The pay range for this position is $80.00 - $80.00/hr.
Eligibility requirements apply to some benefits and may depend on your job classification and length of employment. Benefits are subject to change and may be subject to specific elections, plan, or program terms. If eligible, the benefits available for this temporary role may include the following: • Medical, dental & vision • Critical Illness, Accident, and Hospital • 401(k) Retirement Plan – Pre-tax and Roth post-tax contributions available • Life Insurance (Voluntary Life & AD&D for the employee and dependents) • Short and long-term disability • Health Spending Account (HSA) • Transportation benefits • Employee Assistance Program • Time Off/Leave (PTO, Vacation or Sick Leave)
Workplace Type
This is a fully onsite position in Redmond,WA.
Application Deadline
This position is anticipated to close on Aug 19, 2026.
About Actalent
Actalent is a global leader in engineering and sciences services and talent solutions. We help visionary companies advance their engineering and science initiatives through access to specialized experts who drive scale, innovation and speed to market. With a network of almost 20,000 consultants and 5,000 clients across the U.S., Canada, Asia and Europe, Actalent serves many of the Fortune 500. We are proud to be an Engineering News-Record (ENR) Top 500 Design Firm for our engineering design services and a ClearlyRated Best of Staffing® winner for both client and talent service.
The company is an equal opportunity employer and will consider all applications without regard to race, sex, age, color, religion, national origin, veteran status, disability, sexual orientation, gender identity, genetic information or any characteristic protected by law.
If you would like to request a reasonable accommodation, such as the modification or adjustment of the job application process or interviewing process due to a disability, please email [email protected] for other accommodation options.
San Francisco Fair Chance Ordinance: Pursuant to the San Francisco Fair Chance Ordinance, for all positions located in the city and county of San Francisco, we will consider for employment qualified applicants with arrest and conviction records.
Massachusetts Lie Detector: It is unlawful in Massachusetts to require or administer a lie detector test as a condition of employment or continued employment. An employer who violates this law shall be subject to criminal penalties and civil liability.
Use of Artificial Intelligence (AI): We may use Artificial Intelligence (AI) to support parts of our hiring process, including sourcing, screening, and evaluating candidates. AI helps assess applications and qualifications, but final decisions are made by our hiring team. By applying, you acknowledge and agree that your application may be reviewed using AI tools.
