Rtl Design Engineer Salaries in United States

Using GenAI tools (e.g., large language models, AI-assisted code generation) to design, validate, and optimize SystemVerilog RTL code.

$165,800 - $292,400 a year

Design Reviews: Participate in design reviews and contribute to architecture decisions, not just implementation. Industry experience in ASIC or SoC design.

$205,000 - $285,000 a year

6 days ago

Thoroughly comprehend both internal and external requirements, conducting Power, Performance, and Area (PPA) analysis to optimize design trade-offs.

$110,000 - $300,000 a year

You will develop and implement design verification strategies for both our existing and upcoming ASIC designs. You may be a good fit if you.

$150,000 - $275,000 a year

Build and maintain scripted, automated design flows that streamline synthesis, analysis, and sign-off processes—leveraging AI agents and modern automation tools…

Participate in the full ASIC/FPGA design lifecycle for Starlink projects, from high-level conceptual and architectural discussions through microarchitecture,…

$125,000 - $195,000 a year