Design Verification Engineer Salaries in Austin, TX

As a member of our verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (…

$100,000 - $189,750 a year

4 days ago

Working within a C++ and Verilog/SystemVerilog-based environment, you will independently own a portion of the unit- or core-level verification effort —…

Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB), and methodologies (UVM or equivalent).

$100,000 - $189,750 a year

Drive or support projects that apply formal verification, tools, and techniques to improve hardware design and implementation quality.

Experience leading a technical team, including mentoring, training, and performing technical peer reviews. As a permanent full-time employee of Verilab, you…

Experience in clock-domain-crossing checking, MTBF analysis, either with EDA tools (i.e., Synopsys or Cadence) or in-house tools.

$116,000 - $218,500 a year