Design Verification Engineer Salaries in California

Work on the cutting edge processor design in deep submicron technologies, and on standard cell library design and characterization.

$116,000 - $189,750 a year

Verilog expertise required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis…

$100,000 - $189,750 a year

5 days ago

Exposure to design and verification tools (VCS or equivalent simulator tools; debug tools like Verdi, Debussy, GDB). Expertise in System Verilog and Verilog.

$100,000 - $189,750 a year

Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB), and methodologies (UVM or equivalent).

$116,000 - $218,500 a year

Invent, design, and implement RL environments and evaluations for agentic RTL generation, design (including formal) verification, physical design optimization.

$500,000 - $850,000 a year

9 days ago

In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that…

$226,000 - $445,000 a year