Verification Engineer Salaries in California

Exposure to design and verification tools (VCS or equivalent simulator tools; debug tools like Verdi, Debussy, GDB). Expertise in System Verilog and Verilog.

$100,000 - $189,750 a year

You can explain a technical problem clearly, whether you are writing it up in a bug report or talking through it with a senior engineer who needs context fast.

$90,000 - $136,000 a year

Understand design behavior from specifications, RTL, and discussions with design teams. Passion for formal verification, digital design, computer architecture,…

$100,000 - $189,750 a year

14 days ago

Verilog expertise required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis…

$100,000 - $189,750 a year

6 days ago

Driving positive relationships with account management, field technical, and R&D and marketing organizations. Our customers use our tools and solutions to push…

$293,700 a year

Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and minimum 5 years prior relevant experience or an Advanced Degree in a…

$95,500 - $181,700 a year