Verification Engineer Salaries in Campbell, CA

You can explain a technical problem clearly, whether you are writing it up in a bug report or talking through it with a senior engineer who needs context fast.

$90,000 - $136,000 a year

Exposure to design and verification tools (VCS or equivalent simulator tools; debug tools like Verdi, Debussy, GDB). Expertise in System Verilog and Verilog.

$100,000 - $189,750 a year

Understand design behavior from specifications, RTL, and discussions with design teams. Passion for formal verification, digital design, computer architecture,…

$100,000 - $189,750 a year

14 days ago

Collaborate with hardware design, software/diagnostic, and manufacturing test engineers to develop and execute product test strategies.

From $50 an hour

10 days ago

Verilog expertise required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis…

$100,000 - $189,750 a year

6 days ago

Support frontend, static, and power‑aware design flows, including SystemVerilog, UPF, SDC timing constraints, and static analysis tools (e.g., Lint, CDC, RDC,…