Engineer Salaries in Cupertino, CA

You can explain a technical problem clearly, whether you are writing it up in a bug report or talking through it with a senior engineer who needs context fast.

$90,000 - $136,000 a year

Verilog expertise required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis…

$100,000 - $189,750 a year

6 days ago

In this role, you will impact developing and optimizing manufacturing processes to improve efficiency and productivity, collaborating seamlessly with cross-…

You will utilize engineering skills, hands-on approaches, and work in cross-functional teams to solve production issues, develop processes, and implement…

Exposure to design and verification tools (VCS or equivalent simulator tools; debug tools like Verdi, Debussy, GDB). Expertise in System Verilog and Verilog.

$100,000 - $189,750 a year

You will be responsible for developing and implementing strategies to optimize production processes, driving continuous improvement initiatives, and…