Design Verification Engineer Salaries in Everett, WA

Proven experience optimizing system resources, including compute environments, licensing systems, and infrastructure utilization.

Collaborate effectively with architects, analog mixed-signal designers, verification engineers, and physical design, DFT, and other front-end design teams.

$142,800 - $304,200 a year

Throughout the program lifecycle, you will engage with cross-functional teams—including architecture, quantum, verification, analog, physical design and vendors…

$119,800 - $261,000 a year

You will own the full verification lifecycle, from test planning to coverage closure using SystemVerilog and UVM. 10+ years of ASIC verification experience.

$150,000 - $165,000 a year

University degree in Electrical Engineering or a related field. Proficiency in developing verification environments from scratch.

22 hours ago

You will work across control systems, diagnostics, data infrastructure, operator interfaces, automation, and integration with electrical, mechanical, firmware,…

$185,000 - $240,000 a year