Design Verification Engineer Salaries in Massachusetts

Requirements: Must have a Master’s degree in Computer Science, Computer Engineering, Electrical Engineering, Electronic Engineering, or closely related…

$134,597 - $165,615 a year

Write System Verilog tests and develop UVM environments; perform debug. Communicate technical status and risks to the team leader.

$98,700 - $157,900 a year

SVV is responsible for developing, adopting, and supporting tools, methodologies, and solutions across the entire design verification landscape - including…

$116,960 - $160,820 a year

CGS is seeking an experienced Desktop/Workstation Design Engineer to participate in architecture discussions, system reviews, design planning, and technology…

$116,480 - $158,080 a year

In this role, you will gain end-to-end experience across the digital design lifecycle, including digital system definition; design, simulation, and verification…

$80,000 - $95,000 a year

Develop the verification infrastructure using state of the art verification methodologies and tools. You are encouraged to understand the design and its…

$136,000 - $264,500 a year