Asic Designer Salaries in San Jose, CA

Hands on experience in all aspects of the chip development process with proficiency in front end tools and methodologies. Imagine what you could do here.

11 days ago

Strong in micro-architecture and RTL development (Verilog), as well as entire front-end flows including logic synthesis, power, and timing analysis.

$116,000 - $218,500 a year

Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB), and methodologies (UVM or equivalent).

$116,000 - $218,500 a year

You will own RTL from microarchitecture to tapeout: writing microarchitecture specifications, creating synthesizable SystemVerilog, working with design…

$200,000 - $400,000 a year

This position offers the opportunity to have real impact in a progressive, technology-focused company impacting product lines ranging from consumer graphics to…

$100,000 - $189,750 a year

5 days ago

As a Senior Modeling Engineer, you will collaborate closely with architecture, design, verification, and software teams to develop system models that support…