Design Verification Engineer Salaries in Oregon

System Verilog testbench, Verilog/System Verilog logic design/RTL fluency a must. Regression test development, monitoring, debug/triage, and correction to test…

$127,400 - $236,600 a year

11 days ago

Requirements: Must have a Master’s degree in Computer Science, Computer Engineering, Electrical Engineering, Electronic Engineering, or closely related…

$119,475 - $163,200 a year

Strong knowledge of digital functional simulation, and tools such as Siemens Questa. Work closely with digital design, analog logic, software and verification…

$147,000 - $259,000 a year

Master’s Degree or equivalent in Electrical Engineering/Computer Engineering/Computer Science or closely related field with a minimum of 10 years of relevant…

$154,900 - $247,800 a year

5+ years of logic design experience. AMBA AXI or CHI design experience. Significant ASIC and/or FPGA design experience. Python/Perl/Tcl scripting experience.

$106,900 - $198,500 a year

Works with Program and Project Managers to understand the features, do technical assessment, design, code, test and deliver.