Design Verification Engineer Salaries in Washington State

Skilled in building SVTB/SV UVM/OVM based verification environments and using industry standard HDL languages (e.g., System Verilog) and simulation tools.

$118,500 - $177,500 a year

As a member of our physical design team, you will perform various types of physical verification checks such as LVS, DRC, design-for-manufacturing & design-for-…

$129,300 - $194,700 a year

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP,…

$122,440 - $232,190 a year

Requirements: Must have a Master’s degree in Computer Science, Computer Engineering, Electrical Engineering, Electronic Engineering, or closely related…

$119,475 - $163,200 a year

Experience with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure.

$122,440 - $232,190 a year

11 days ago

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

$163,000 - $237,000 a year