Verification Engineer Salaries in Washington State

As a member of our physical design team, you will perform various types of physical verification checks such as LVS, DRC, design-for-manufacturing & design-for-…

$129,300 - $194,700 a year

Skilled in building SVTB/SV UVM/OVM based verification environments and using industry standard HDL languages (e.g., System Verilog) and simulation tools.

$118,500 - $177,500 a year

Interpret simulation results using tools such as Simvision to root cause discrepancies between expected and simulated results in collaboration with the design…

$70,304 - $205,000 a year

Bachelor’s degree in software, engineering, computer science, or another related field. This role supports our engineering and manufacturing operations and is…

$85,000 - $110,000 a year

Develop and document formal verification test plans and conduct technical reviews with design and architecture teams. Shift 1 (United States of America).

$164,470 - $311,890 a year

Experience with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure.

$122,440 - $232,190 a year

9 days ago