Top 54 Engineering lead Jobs in Aptos, Ca

Lead ASIC DFT Engineer
Cyient —San Jose, CA
- $80 - $85 an hour
- Full-time
- Analysis skills
- Mentoring
- In-person
Quick Apply
Product Manager - CAD Engineering Lead
Specialized —Morgan Hill, CA
- Full-time
- ERP systems
- System design
- Training & development
Performance Lead/DER
Joby Aviation —Santa Cruz, CA
- $126,000 - $277,000 a year
- Full-time
- Bachelor of Science
- Engineering
- Data analysis skills
- Employee stock purchase plan
- Disability insurance
Lead Software Engineer, Ads (Remote)
Jane Technologies —Santa Cruz, CA
- $175,000 - $195,000 a year
- Full-time
- Remote
- 6 years
- Computer Science
- System design
Quick Apply
Lead Photonics System Engineer
Advanced Micro Devices, Inc —San Jose, CA
- Hybrid work
- Master's degree
- Bachelor's degree
- Mentoring
Lead Electrical Systems Engineer
Leidos —California
- $131,300 - $237,350 a year
- Full-time
- Hybrid work
- Engineering
- Master's degree
- Team management
4d
Lead Electrical Systems Engineer
Leidos —California
- $131,300 - $237,350 a year
- Full-time
- Hybrid work
- Engineering
- Master's degree
- Team management
4d
Lead Electrical Systems Engineer
Leidos —California
- $131,300 - $237,350 a year
- Full-time
- Hybrid work
- Engineering
- Master's degree
- Team management
4d
Lead Compliance Engineer
Heron Power —Scotts Valley, CA
- $150,000 - $198,000 a year
- Full-time
- 7 years
- Research
- Master's degree
Design Verification Lead
Advanced Micro Devices, Inc —San Jose, CA
- Hybrid work
- Computer Science
- Master's degree
- Analysis skills
5d
Aircraft Final Integration Manufacturing Engineering Lead
Joby Aviation —Marina, CA
- $137,400 - $188,900 a year
- Overtime
- 3 years
- Assembly
- Bachelor's degree
- Employee stock purchase plan
- Disability insurance
Lead Embedded Systems Software Engineer
E-Space —Saratoga, CA
- $150,000 - $225,000 a year
- Weekends as needed
- 7 years
- Office
- Mentoring
- Paid holidays
- Paid time off
FPGA Prototyping Lead
Advanced Micro Devices, Inc —San Jose, CA
- Hybrid work
- 11+ years
- Master's degree
- Mentoring
6d
Flight Test Engineering Lead
Joby Aviation —Marina, CA
- $188,000 - $242,000 a year
- Extended hours
- Bachelor of Science
- English
- Analysis skills
- Employee stock purchase plan
- Disability insurance
5G Core System Engineering Lead
E-Space —Saratoga, CA
- $180,000 - $220,000 a year
- Weekends as needed
- Computer Science
- Office
- Master's degree
- Paid holidays
- Paid time off
Sr. Engineering Leader: Developer SDKs for Embedded Markets
Advanced Micro Devices, Inc —San Jose, CA
- Hybrid work
- Computer science
- Computer Science
- Bachelor of Science
Software Development Engineering Lead- Routing
Advanced Micro Devices, Inc —San Jose, CA
- Hybrid work
- Computer Science
- Master's degree
- Doctor of Philosophy
Engineering Design Lead
ArchKey Solutions LLC —San Jose, CA
- $128,000 - $153,600 a year
- Weekends as needed
- Engineering
- 11+ years
- Office
- Paid holidays
- Health insurance
Quick Apply
Flight Research Embedded Systems Lead
Joby Aviation —Santa Cruz, CA
- Full-time
- 6 years
- System design
- Master's degree
- Employee stock purchase plan
- Disability insurance
ASIC Chip Design Lead
Eridu AI —Saratoga, CA
- $250,000 - $280,000 a year
- Full-time
- Analysis skills
- Senior level

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engineering lead jobs near aptos, ca

Lead ASIC DFT Engineer

Cyient -
San Jose, CA

Quick Apply

Job Details

Full-time | Contract
$80 - $85 an hour

Qualifications

Analog circuit design
Engineering development testing
Electronics functional testing
Integrated circuits (ICs)
Ramps
Analysis skills
SoC
System architecture design
Simulation tools
Root cause analysis
Test analysis
Python
Debugging
Cross-functional communication

Full Job Description

Title - Lead ASIC DFT Engineer

Location – San Jose, CA.

Duration - Contract

Job Description

Experience

10+ years of hands-on experience in ASIC Design-for-Test (DFT)

Role Summary

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.

The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.

Key Responsibilities

Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
Act as a technical escalation point for advanced DFT and post-silicon debug issues.
Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.

Required Skills & Qualifications

Strong hands-on experience in ASIC DFT with end-to-end ownership.
Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
Experience with MBIST implementation and verification; SMS experience preferred.
Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
Proven post-silicon debug and silicon bring-up experience.
Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
Strong communication skills and the ability to work independently with minimal ramp-up.

Preferred Experience

MBIST post-silicon validation.
ATPG simulations and fault coverage debug.
DFT RTL, DFD, DFT verification, and IP-level DFT integration.
DFT SDC creation and DFT timing closure support.
Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
TCL/PERL scripting for DFT automation, reporting, and debug.
Experience working across multiple ASIC technology nodes and complex product development cycles.
Familiarity with yield learning, diagnosis, and manufacturing test optimization.

Pay: $80.00 - $85.00 per hour

Work Location: In person

Quick Apply

Refine Your Search

engineering lead jobs in aptos, ca

Lead ASIC DFT Engineer

Product Manager - CAD Engineering Lead

Performance Lead/DER

Lead Software Engineer, Ads (Remote)

Lead Photonics System Engineer

Lead Electrical Systems Engineer

Lead Electrical Systems Engineer

Lead Electrical Systems Engineer

Lead Compliance Engineer

Design Verification Lead

Aircraft Final Integration Manufacturing Engineering Lead

Lead Embedded Systems Software Engineer

FPGA Prototyping Lead

Flight Test Engineering Lead

5G Core System Engineering Lead

Sr. Engineering Leader: Developer SDKs for Embedded Markets

Software Development Engineering Lead- Routing

Engineering Design Lead

Flight Research Embedded Systems Lead

ASIC Chip Design Lead

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