Top 20 Serdes architect Jobs in Austin Tx

Serdes System Design Engineer/Architect
Broadcom —Austin, TX
- $108,000 - $192,000 a year
- Full-time
- 6 years
- Engineering
- Fair chance
- Employee stock purchase plan
- Paid holidays
Senior Serdes System Design Engineer/Architect
Broadcom —Austin, TX
- $108,000 - $192,000 a year
- Full-time
- 6 years
- Bachelor of Science
- Fair chance
- Employee stock purchase plan
- Paid holidays
ASIC Design Verification Engineer
Ericsson —Austin, TX
- 8 hour shift
- Hybrid work
- Master's degree
- Linux
- In-person
- Paid parental leave
- AD&D insurance
Hardware Engineering Architect, Server/Remote/Hybrid
Jabil Circuit —Austin, TX
- Full-time
- Remote
- Schematics
- 11+ years
- English
Director of Design Verification
Marvell —Austin, TX
- $197,400 - $292,150 a year
- Current TB test
- Computer Science
- 11+ years
- Employee stock purchase plan
Senior SerDes Architect and Lead
Omni Design Technologies —Austin, TX
- Full-time
- Laboratory experience
- Analysis skills
- Senior level
Senior/Staff Analog Design Engineer - SerDes
OLIX —Austin, TX
- $317,000 a year
- Full-time
- Schematics
- Office
- Residential
- Retirement plan
Physical Design Engineer
OLIX —Austin, TX
- From $305,000 a year
- Full-time
- Office
- Residential
- US work authorization
- Retirement plan
SOC IP Methodology Engineer - Custom SOC
NVIDIA —Austin, TX
- $168,000 - $310,500 a year
- Full-time
- Bachelor of Science
- System design
- Master's degree
AMS Engineer
OLIX —Austin, TX
- From $264,000 a year
- Full-time
- 5 years
- Bachelor of Science
- Office
- Retirement plan
Hardware Engineering Architect, Networking Devices
Jabil Circuit —Austin, TX
- Full-time
- Hybrid work
- Schematics
- 11+ years
- English
CAD/EDA Manager
Neurophos —Austin, TX
- $220,000 - $255,000 a year
- Full-time
- CAD
- Bachelor of Science
- 8 years
- Health savings account
- Health insurance
Quick Apply
Principal Firmware Engineer
Cadence Design Systems —Austin, TX
- Full-time
- APIs
- Senior level
Senior Staff Design Verification Engineer
Marvell —Austin, TX
- $135,900 - $201,130 a year
- Full-time
- Computer Science
- 3 years
- Master's degree
- Employee stock purchase plan
Senior/Staff Digital Design Engineer
OLIX —Austin, TX
- $194,000 a year
- Full-time
- Residential
- Mentoring
- US work authorization
- Retirement plan
Senior/Staff Design for Test Engineer
OLIX —Austin, TX
- $321,000 a year
- Full-time
- Office
- Residential
- Mentoring
- Retirement plan
Principal Signal Power Integrity Engineer, Texas Institute for Electronics
University of Texas at Austin —Austin, TX
- $854,197 a year
- Weekends as needed
- Hybrid work
- Bachelor of Science
- 11+ years
- Office
- Paid holidays
- Disability insurance
Principal Mixed Signal Engineer, Texas Institute for Electronics
University of Texas at Austin —Austin, TX
- Full-time
- Hybrid work
- 11+ years
- Research
- Office
- Paid holidays
- Disability insurance
Senior UCIe PHY Expert, MLA Technology
Annapurna Labs (U.S.) Inc. —Austin, TX
- $159,200 - $215,300 a year
- Full-time
- 7 years
- Computer Science
- System design
- AD&D insurance
- Health insurance
Sr. SoC RTL Design Engineer, AI Hardware
Tesla —Austin, TX
- Full-time
- Computer science
- Computer Science
- 5 years
- Commuter assistance
- Health savings account

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serdes architect jobs near austin tx

Serdes System Design Engineer/Architect

Broadcom -
Austin, TX

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Job Details

Full-time
$108,000 - $192,000 a year

Benefits

Employee stock purchase plan
Paid holidays
Health insurance
Dental insurance
Family leave
Employee assistance program
Vision insurance
401(k) matching
Paid sick time

Qualifications

Digital signal processing
MATLAB
Digital circuit design
C

Full Job Description

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Job Description:

Job Description:
This is a DSP/Systems Design Engineering position for high-speed Serdes products in the Physical Layer Products (PLP) Division. You will join a team of expert communication system/mixed-signal ASIC designers involved in the design, verification, and implementation of advanced signal processing algorithms for the physical layer of high-speed Serdes at speeds of 100G+.
The types of algorithms that will be implemented include PAM & other higher-order modulation, single/multi-input adaptive equalizers/cancellers, single/multi-dimensioned FEC, digital filters, and interface/integration with analog functions and analysis and compensation for analog circuit non-idealities.
You will be collaborating closely with analog & digital designers to successfully implement the algorithms in advanced silicon technology nodes and work with DVT/lab engineers to validate your designs for high-volume production.
You will support the group contribute to the development of next-generation wireline communications standards at standard bodies such as IEEE and OIF.

Responsibilities include:

Develop channel models and run simulations to help define Serdes architecture
Define and document signal processing block requirements, architecture, and lab test plan
Develop bit-exact MATLAB and C/C++ system models for simulation and verification
Develop and run system-level simulation suites of the Serdes to evaluate architectural tradeoffs
Work with the design team to perform vector matching verification with RTL simulations
Develop, test, and debug firmware associated with physical layer functionality
Lab testing and debug of Serdes
Documentation/application note development and customer support
Support marketing group with customer meetings and collateral

Job Requirements

Bachelors in Engineering and 8+ years of related experience; at this level postgraduate coursework may be desirable or Masters degree in Engineering and 6+ years of related experience
Expert knowledge in Communication Theory
Expert knowledge in Digital Signal Processing algorithms
Working knowledge of Analog circuit behavior
Working knowledge of Transmission line theory and s-parameter
Expert in MATLAB, C/C++ programming
Good hands-on skills in the lab
Experience in designing high-speed Clock and Data Recovery (CDR) PLLs is a very big plus.
Experience in equalization techniques for wireline communication applications such as read-channel is also a very big plus.
RTL coding is a plus
Knowledge of IEEE 802.3/OIF 100G/200G/400G Serdes standards and PCIe Gen6/Gen7 standards is a plus

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is $108,000 - $192,000.

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Apply Now

Refine Your Search

serdes architect jobs in austin tx

Serdes System Design Engineer/Architect

Senior Serdes System Design Engineer/Architect

ASIC Design Verification Engineer

Hardware Engineering Architect, Server/Remote/Hybrid

Director of Design Verification

Senior SerDes Architect and Lead

Senior/Staff Analog Design Engineer - SerDes

Physical Design Engineer

SOC IP Methodology Engineer - Custom SOC

AMS Engineer

Hardware Engineering Architect, Networking Devices

CAD/EDA Manager

Principal Firmware Engineer

Senior Staff Design Verification Engineer

Senior/Staff Digital Design Engineer

Senior/Staff Design for Test Engineer

Principal Signal Power Integrity Engineer, Texas Institute for Electronics

Principal Mixed Signal Engineer, Texas Institute for Electronics

Senior UCIe PHY Expert, MLA Technology

Sr. SoC RTL Design Engineer, AI Hardware

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