Top 121 Integrity engineer Jobs in Boise, Id

Senior Principal ASIC FPGA Engineer
General Dynamics Mission Systems, Inc —Boise, ID
- $191,146 - $212,053 a year
- Full-time
- Hybrid work
- Master's degree
- 8 years
- Analysis skills
4d
Field Service Engineer I (semiconductor)
Canon U.S.A., Inc. —Boise, ID
- $27.88 - $41.75 an hour
- Full-time
- Clean driving record
- Customer service
- Bachelor of Science
- Profit sharing
- COVID-19 protective measures
Quick Apply
10d
Signal and Power Integrity Lab Engineer
Micron —Boise, ID
- Bachelor of Science
- Mid-level
- 3 years
- Employee stock purchase plan
- Paid holidays
New College Grad - ENGINEER - PYE
Micron —Boise, ID
- Night shift
- Bachelor of Science
- Analysis skills
- Organizational skills
- Employee stock purchase plan
- Paid holidays
Data Solutions Engineer I or II
Blue Cross of Idaho —Meridian, ID
- $78,064 - $144,275 a year
- Full-time
- Hybrid work
- Computer Science
- Research
- Mid-level
- Paid holidays
- Disability insurance
4d
Product Yield Enhancement Engineer
Micron —Boise, ID
- Night shift
- Mid-level
- Analysis skills
- Organizational skills
- Employee stock purchase plan
- Paid holidays
Sr. Applications Engineer
Axcelis Technologies Inc. —Boise, ID
- $126,639.20 - $189,958.80 a year
- Full-time
- Master's degree
- Supervising experience
- Math
Quick Apply
Senior Engineer, Tailings and Closure
Teck —Idaho
- $101,000 - $131,000 a year
- Full-time
- Hybrid work
- Analysis skills
- Travel
- Experience equivalent to degree accepted
- Paid holidays
- Disability insurance
Associate Controls Engineer
Wunderlich-Malec Engineering, Inc —Boise, ID
- Full-time
- Hybrid work
- Microsoft Excel
- Microsoft Outlook
- Computer literacy
- Travel reimbursement
- Profit sharing
Quick Apply
Associate Controls Engineer
Wunderlich-Malec Engineering, Inc. —Boise, ID
- Full-time
- Hybrid work
- Microsoft Excel
- Microsoft Outlook
- Computer literacy
- Travel reimbursement
- Profit sharing
Change Management Engineer
Micron —Boise, ID
- Engineering
- Mid-level
- Team management
- Employee stock purchase plan
- Paid holidays
Project Engineer
ACCO Engineered Systems —Boise, ID
- Overtime
- Microsoft Excel
- Construction site
- Bachelor of Science
- Employee stock ownership plan
Field Service Engineer II - PVD Semiconductor
Canon U.S.A., Inc. —Boise, ID
- $29.20 - $43.73 an hour
- 12 hour shift
- Clean driving record
- Bachelor of Science
- English
- Profit sharing
- COVID-19 protective measures
Cloud DB Architect / ML & Agentic AI Engineer
Knuff & Kunde CPAs —Eagle, ID
- Part-time
- Hybrid work
- APIs
- Linux
- Senior level
- Health savings account
- Health insurance
Quick Apply
5d
dbt Engineer
Blue Cross of Idaho —Meridian, ID
- $96,183 - $177,758 a year
- Full-time
- Hybrid work
- Mid-level
- Office
- SQL
- Paid holidays
- Disability insurance
Project Engineer
HC Company Inc. —Boise, ID
- From $90,000 a year
- Construction site
- Mid-level
- Business development
Quick Apply
5d
Software Development Engineer
Clearwater Analytics, LLC —Boise, ID
- Full-time
- Computer science
- Computer Science
- Mid-level
Quick Apply
Mid-Level Electrical Engineer (Generation)
WSP —Boise, ID
- $86,100 - $150,590 a year
- Construction site
- 5 years
- Engineering
- Paid parental leave
- Disability insurance
New College Grad - Semiconductor Design Engineer
Micron —Boise, ID
- CAD
- Master's degree
- Analysis skills
- Employee stock purchase plan
- Paid holidays
5d
Field Service Engineer, Advanced
Keysight Technologies, Inc. —Boise, ID
- $80,700 - $134,500 a year
- Overtime
- Clean driving record
- Up to 50% travel
- 5 years
- Health savings account
- Employee stock purchase plan

I want to receive the latest job alert for integrity engineer in boise, id

By signing in to your account, you agree to SimplyHired's Terms of Service and consent to our Cookie and Privacy Policy.

Explore jobs in more locations

integrity engineer jobs near boise, id

Senior Principal ASIC FPGA Engineer

General Dynamics Mission Systems, Inc -
Boise, ID

Apply Now

Job Details

Full-time
$191,146 - $212,053 a year
4 days ago

Qualifications

Jira
Project reporting
Vendor selection
Defect resolution root cause analysis
Bug Tracking (Quality assurance practices)
Bachelor's degree in electrical engineering
Tooling
FPGA
Triage
Electronics test plan development
Engineering process optimization
Process improvement
Master's degree
8 years
System design for system development
Team development
Schedule management
Collaboration with product development teams
Analysis skills
Documentation tools
Bachelor's degree in engineering
Managing engineering teams
Design development
System validation
Product backlog management
Issue tracking
Mentoring
Design engineering
Computer Engineering
Vendor communication

Full Job Description

Basic Qualifications :

Education Requirements:

Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 10 years of relevant experience; or Master's degree plus a minimum of 8 years of relevant experience.

Clearance Requirements:

Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.

Responsibilities for this Position:

We're looking for a seasoned ASIC Lead Engineer who has been there — not just written RTL, but fought through timing closure under pressure, untangled bus fabric correctness issues, debugged reset sequencing nightmares, and brought complex silicon to tape-out. This is a hands-on technical leadership role for someone who has lived the full ASIC design lifecycle and has the scars to prove it.

If your career has been primarily running P&R tools, this probably isn't the right fit. We need an RTL designer at heart — someone who thinks in architecture and microarchitecture first, and understands the downstream implications of every design decision.

The right candidate is a self-starter who operates with minimal supervision — someone who takes ownership of their domain, drives progress independently, and brings solutions rather than waiting to be directed. You'll be well-integrated within a collaborative team, but we expect you to lead from the front, not follow from behind.

What You'll Do

Own the architecture — Define the ASIC/FPGA technical approach from concept through silicon, including system
partitioning, microarchitecture, and interface definition
Drive RTL design — Lead detailed RTL development with a focus on correctness: bus fabric integrity, clock domain
crossings, reset order-of-operations, and design-for-verification
Close timing — Navigate synthesis, place and route, and static timing analysis with deep understanding of what it
takes to meet timing in advanced process nodes — not just run the tools, but fix the problems
Lead verification — Serve as the primary point of contact for verification activities; develop and own test and
simulation plans that establish rigorous functional criteria; verify results and drive closure on failures
Triage and track — Own JIRA triage for the team: reviewing incoming issues, prioritizing work items, and ensuring
the backlog reflects program reality
Lead code reviews — Conduct and lead RTL code reviews, setting the technical bar and providing actionable, constructive feedback to engineers at all levels
Support program planning — Contribute to Integrated Master Schedule (IMS) development and Earned Value (EV)
reporting; provide accurate technical input on task status, completion criteria, and schedule risk
Evaluate process flows — High-level design through GDSII, including synthesis, P&R, timing, power analysis, and DFT considerations
Guide technology selection — Assess foundry technologies, device libraries, IP cores, and EDA tooling to inform
design decisions
Support proposals and subcontracts — Lead ASIC/FPGA technical approach on large proposals; may serve as book boss on medium proposals; manage technical subcontracts including SOW development, source selection, and work product
acceptance
Grow the team — Mentor junior and mid-level engineers; contribute to the development and improvement of
organizational ASIC/FPGA design processes
Collaborate broadly — Participate in multi-divisional or multi-company Integrated Product Teams and working groups

What We're Looking For

Experience

10–15+ years of ASIC/FPGA design experience, with the majority spent as an RTL designer — not in a purely backend or physical design role
Proven experience taking designs through full ASIC tape-out, including timing closure, physical verification, and
post-silicon bring-up
Deep familiarity with FinFET process nodes (7nm, 5nm, or similar) — understanding the nuances of FinFET vs. planar
technology is a meaningful differentiator for this role
Experience with commercial foundry flows (TSMC, GlobalFoundries, Samsung, or equivalent)
Demonstrated expertise in:
- RTL design and microarchitecture definition
- Bus fabric design and correctness verification
- Clock domain crossing (CDC) analysis and closure
- Reset sequencing and order-of-operations validation
- Timing closure at advanced nodes — not just constraint writing, but root cause analysis and fixing
- Power analysis and optimization

Skills & Knowledge

Expert-level understanding of ASIC/FPGA engineering concepts, RTL coding practices, and synthesis flows
Strong familiarity with industry-standard EDA tools (synthesis, simulation, formal verification, STA)
Demonstrated ability to operate independently — identifying problems, driving resolution, and keeping work moving
without requiring day-to-day direction
Ability to evaluate vendor and foundry capabilities to support product development decisions
Track record of innovative technical contributions — not just executing to spec, but shaping the approach
Solid understanding of organizational processes and the ability to apply them pragmatically across a program
lifecycle, including schedule management and earned value inputs
Proficiency in JIRA for issue tracking and backlog management
Proficiency in Microsoft Office for documentation and communication

Why This Role
You won't be handed a spec and told to code. You'll help shape what we build, how we build it, and what it takes to get it right. This is a role with real technical latitude, the kind of program impact that shows up in new business, and a team that values engineers who know the difference between running the tools and knowing what the tools are telling you. If you're the kind of engineer who sees a gap and fills it — without being asked — this is the role for you.

#LI-JH1

#LI-Hybrid

Salary Note: This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled. Combined Salary Range: USD $191,146.00 - USD $212,053.00 /Yr. Company Overview:

General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team!

Equal Opportunity Employer / Individuals with Disabilities / Protected Veterans

Apply Now

Refine Your Search

integrity engineer jobs in boise, id

Senior Principal ASIC FPGA Engineer

Field Service Engineer I (semiconductor)

Signal and Power Integrity Lab Engineer

New College Grad - ENGINEER - PYE

Data Solutions Engineer I or II

Product Yield Enhancement Engineer

Sr. Applications Engineer

Senior Engineer, Tailings and Closure

Associate Controls Engineer

Associate Controls Engineer

Change Management Engineer

Project Engineer

Field Service Engineer II - PVD Semiconductor

Cloud DB Architect / ML & Agentic AI Engineer

dbt Engineer

Project Engineer

Software Development Engineer

Mid-Level Electrical Engineer (Generation)

New College Grad - Semiconductor Design Engineer

Field Service Engineer, Advanced

I want to receive the latest job alert for integrity engineer in boise, id

Related Searches

Explore jobs in more locations

Job Seeker Tools

Employer Tools

Browse

Stay Connected