Job Title: IC Package Design Manager – ASIC Engineer
Job Description
This role leads a team of engineers designing complex flip‑chip BGA packages for advanced ASICs that power artificial intelligence, networking, high‑performance computing, and 5G base stations. You will manage and mentor a worldwide R&D team, drive high‑performance package designs featuring cutting‑edge SerDes, high‑bandwidth memory, and advanced power delivery, and shape technical methodologies and project management practices for multiple concurrent programs.
Responsibilities
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Lead and manage a team of IC package design engineers focused on complex flip‑chip BGA packages for industry‑leading ASICs.
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Oversee and contribute to the design of packages that support high‑speed SerDes (448G and higher), 5G RF/microwave ADC/DAC, HBM, DDR5, and very high power delivery requirements.
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Create, maintain, and track project plans for 20+ concurrent package designs, including defining scope, schedules, and resource allocation.
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Organize team and customer activities to keep projects on schedule, ensuring alignment across engineering, customers, and vendors.
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Communicate project plans, status, next steps, and risks clearly and regularly to stakeholders across multiple time zones.
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Develop and refine technical methodologies for package design, including best practices, standards, and workflows.
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Steer package technology choices and design rules in collaboration with team members and cross‑functional partners.
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Apply deep knowledge of package‑level signal integrity and power integrity to guide and review package designs.
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Collaborate with a worldwide R&D team, coordinating co‑design activities with internal team members and external vendor designers.
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Oversee and support the full package‑design lifecycle, from concept and architecture through layout, verification, and release.
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Ensure that substrate and package designs integrate seamlessly into overall ASIC design and manufacturing flows.
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Manage and review design data, including .mcm files, package spreadsheets, and drawings such as POD, lid, and substrate documentation.
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Evaluate and balance DFx trade‑offs (design for manufacturability, reliability, assurance of supply, signal integrity, power integrity, and other factors) in package designs.
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Guide and review layout activities, ensuring adherence to design rules and performance targets.
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Direct and interpret SI/PI extractions and simulations to validate and optimize package performance.
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Promote and support automation code development to improve design efficiency, quality, and repeatability.
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Oversee mechanical and thermal modeling of packages to ensure robust operation under target conditions.
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Participate in and support new business quotation activities related to package design, including effort estimation and technical input.
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Collaborate closely with customers, vendors, and cross‑functional teams (such as PCB layout and ASIC design teams) to ensure cohesive solutions.
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Understand the skill sets and strengths of each team member to maximize productivity, engagement, and retention.
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Encourage strong self‑management and organizational practices within the team, fostering accountability and ownership.
Essential Skills
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BSEE, MSEE, or a similar degree in an appropriate engineering field.
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12+ years of experience in flip‑chip BGA package design, including high‑speed SerDes applications.
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Minimum of 3 years of management experience leading engineering teams and projects.
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Hands‑on experience with flip‑chip package design for ASICs, including complex power delivery requirements.
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Strong knowledge of high‑speed SerDes design considerations within package environments (including 448G and higher).
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Proficiency in package‑level signal integrity (SI) and power integrity (PI) and their application to real‑world package designs.
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Experience with the complete package‑design lifecycle, from concept through release to manufacturing.
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Understanding of how substrate and package designs fit into overall ASIC design and manufacturing flows.
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Ability to work effectively with worldwide teams across multiple time zones.
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Strong project management skills, including creating and tracking detailed project plans for multiple concurrent designs.
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Proven ability to communicate plans, status, next steps, and risks clearly to technical and non‑technical stakeholders.
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Demonstrated self‑management and organizational skills in a complex engineering environment.
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Experience with PCB layout and its interaction with ASIC package and chip design.
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Solid understanding of ASIC chip and package co‑design principles.
Additional Skills & Qualifications
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Previous experience managing both people and technical projects in an IC packaging or related domain.
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Familiarity with design data formats and artifacts such as .mcm files, package spreadsheets, and drawings (POD, lid, substrate).
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Experience evaluating DFx (design for manufacturability, reliability, assurance of supply, SI/PI, and related factors) trade‑offs in package design.
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Experience in layout processes and tools used for advanced IC package design.
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Experience performing or overseeing SI/PI extractions and simulations for high‑speed and high‑power packages.
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Exposure to automation code development to streamline and standardize design workflows.
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Experience with mechanical and thermal modeling of IC packages.
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Involvement in new business quotation activities related to package design and development.
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Strong customer, vendor, and cross‑functional collaboration skills, particularly with PCB layout and ASIC design teams.
Work Environment
This is an onsite role based primarily in Fort Collins, with secondary onsite preference for locations such as San Jose. You will work closely with a worldwide R&D organization across multiple time zones, collaborating with internal teams and external vendor designers. The environment focuses on advanced IC packaging technologies for AI, networking, HPC, and 5G applications, using modern design, simulation, and automation tools to deliver high‑performance, high‑reliability solutions.
Job Type & Location
This is a Permanent position based out of Broomfield, CO.
Pay and Benefits
The pay range for this position is $140000.00 - $240000.00/yr.
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Workplace Type
This is a fully onsite position in Broomfield,CO.
Application Deadline
This position is anticipated to close on Aug 5, 2026.
About Actalent
Actalent is a global leader in engineering and sciences services and talent solutions. We help visionary companies advance their engineering and science initiatives through access to specialized experts who drive scale, innovation and speed to market. With a network of almost 20,000 consultants and 5,000 clients across the U.S., Canada, Asia and Europe, Actalent serves many of the Fortune 500. We are proud to be an Engineering News-Record (ENR) Top 500 Design Firm for our engineering design services and a ClearlyRated Best of Staffing® winner for both client and talent service.
The company is an equal opportunity employer and will consider all applications without regard to race, sex, age, color, religion, national origin, veteran status, disability, sexual orientation, gender identity, genetic information or any characteristic protected by law.
If you would like to request a reasonable accommodation, such as the modification or adjustment of the job application process or interviewing process due to a disability, please email [email protected] for other accommodation options.
San Francisco Fair Chance Ordinance: Pursuant to the San Francisco Fair Chance Ordinance, for all positions located in the city and county of San Francisco, we will consider for employment qualified applicants with arrest and conviction records.
Massachusetts Lie Detector: It is unlawful in Massachusetts to require or administer a lie detector test as a condition of employment or continued employment. An employer who violates this law shall be subject to criminal penalties and civil liability.
Use of Artificial Intelligence (AI): We may use Artificial Intelligence (AI) to support parts of our hiring process, including sourcing, screening, and evaluating candidates. AI helps assess applications and qualifications, but final decisions are made by our hiring team. By applying, you acknowledge and agree that your application may be reviewed using AI tools.
