Top 45 Debug soc design engineer Jobs in Irvine, Ca

Debug SoC Design Engineer
Apple —Irvine, CA
- $122,700 - $214,300 a year
- Bachelor's degree
- Senior level
- Employee stock purchase plan
- Health insurance
RFIC Design Engineer
Apple —Irvine, CA
- $175,000 - $308,500 a year
- Bachelor of Science
- Master's degree
- Analysis skills
- Employee stock purchase plan
- Health insurance
Wireless SOC Verification Engineer
Apple —Irvine, CA
- $122,700 - $214,300 a year
- Analysis skills
- Bachelor's degree
- Senior level
- Employee stock purchase plan
- Health insurance
Wireless Design Verification Engineer
Apple —Irvine, CA
- $175,000 - $308,500 a year
- Bachelor of Science
- Analysis skills
- Bachelor's degree
- Employee stock purchase plan
- Health insurance
Digital Design Engineer (MPU)
BrainChip, Inc. —Laguna Hills, CA
- Hybrid work
- Mid-level
- 3 years
- Python
Quick Apply
Sr. Staff Design Verification Engineer
Marvell —Irvine, CA
- $135,900 - $201,130 a year
- 7 years
- Bachelor of Science
- Senior level
- Employee stock purchase plan
RFIC Test Engineer
Apple —Irvine, CA
- $175,000 - $308,500 a year
- Bachelor of Science
- Bachelor's degree
- Senior level
- Employee stock purchase plan
- Health insurance
Senior Staff Digital Design Engineer
Marvell —Irvine, CA
- $135,900 - $201,130 a year
- Full-time
- Bachelor of Science
- Continuous improvement
- Doctor of Philosophy
- Employee stock purchase plan
Senior Staff Engineer, ASIC/VLSI Synthesis and Design
Marvell —Irvine, CA
- $135,900 - $201,130 a year
- Full-time
- Computer Science
- 5 years
- Master's degree
- Employee stock purchase plan
Wireless Systems Integration Engineer
Apple —Irvine, CA
- $175,000 - $308,500 a year
- Bachelor of Science
- Master's degree
- Analysis skills
- Employee stock purchase plan
- Health insurance
Senior Staff Design Verification Engineer – PCIE/CXL Sub-System
Marvell —Irvine, CA
- $135,900 - $201,130 a year
- 5 years
- Master's degree
- Mentoring
- Employee stock purchase plan
Security Firmware Engineer
Sandisk —Irvine, CA
- Full-time
- Hybrid work
- Computer Science
- Mid-level
- Master's degree
- Health savings account
- AD&D insurance
Quick Apply
Senior Staff Design Engineer - PCIE/CXL Subsystem COE
Marvell —Irvine, CA
- $135,900 - $201,130 a year
- Master's degree
- Mentoring
- Senior level
- Employee stock purchase plan
Field Application Engineer – PowerPro
Siemens —Costa Mesa, CA
- $146,700 - $293,400 a year
- Full-time
- Hybrid work
- Bachelor of Science
- Mid-level
- Analysis skills
Wireless System Integration and Characterization Engineer
Apple —Irvine, CA
- $175,000 - $308,500 a year
- Bachelor of Science
- System design
- 3 years
- Employee stock purchase plan
- Health insurance
Senior Staff Engineer, ASIC Design/Implementation -- LEC/STA/Power Analysis
Marvell —Irvine, CA
- $135,900 - $201,130 a year
- Full-time
- Computer Science
- 5 years
- Master's degree
- Employee stock purchase plan
R&D Applications Engineer, Emulex Connectivity Division (ECD)
Broadcom —Irvine, CA
- $108,000 - $172,800 a year
- Full-time
- 6 years
- Bachelor of Science
- Master's degree
- Employee stock purchase plan
- Paid holidays
Principal Analog and Mixed-Signal IC Design Engineer
Marvell —Irvine, CA
- $176,500 - $261,180 a year
- Full-time
- Computer Science
- 5 years
- Master's degree
- Employee stock purchase plan
FPGA Verification Engineer, Air Vehicles
Anduril Industries —Costa Mesa, CA
- $123,000 - $171,000 a year
- Email
- Mid-level
- Master's degree
- Linux
Quick Apply
Sr. Full Chip Physical Verification Engineer (Silicon Engineering)
SpaceX —Irvine, CA
- $165,000 - $260,000 a year
- Extended hours
- Computer science
- Computer Science
- Senior level
- Paid parental leave
- Employee stock purchase plan

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Debug SoC Design Engineer

Apple -
Irvine, CA

Apply Now

Job Details

$122,700 - $214,300 a year

Benefits

Employee stock purchase plan
Health insurance
Dental insurance
RSU
Retirement plan

Qualifications

Semiconductor electronics
Verilog
SoC
Digital circuit design
Bachelor's degree
Digital design

Full Job Description

Come and join Apple’s growing wireless silicon development team. Our wireless SoC organization is responsible for all aspects of wireless silicon development, emphasizing highly energy-efficient design and new technologies that transform the user experience at the product level. All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. If you enjoy a fast-paced and challenging environment, collaborate with people across different functional areas, and thrive during crisis times, we encourage you to apply.

Description

In this role you will work on a small team designing CPU-based subsystems for high performance, low power wireless SoCs. You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals.

You will own the design for the debug and trace hub. You will collaborate with other designers to ensure their subsystems implement the necessary debug features. You will guide validation engineers in the use of such features to diagnose issues. This is a highly visible role, where you will be at the center of the ASIC debug efforts, collaborating with all fields, with a critical impact in getting leading-edge products launched to delight millions of customers.","responsibilities":"RTL ownership of debug and trace hub - development, assessment, and refinement of RTL design to target power, performance, area and timing goals.

Micro-architecture development and specification - Work with a cross-functional team of silicon and software experts to explore and define architectural debug features, develop micro-architectural details, and arrive at a detailed specification.

Verification - support the verification team in test bench development and simulation/emulation for functional verification of debug features.

Performance/power correlation - assist performance/power teams to diagnose suspected bottlenecks or overconsumption.

Validation - Aid in debug of silicon issues at SoC level by employing the necessary debug features

Collaboration with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality by incorporating proper checks at every stage of the design process.

Preferred Qualifications

Knowledge and understanding of microprocessor debug such as CoreSight and other debug techniques.

Shown experience writing micro-architecture specifications and converting them to design.

Experience with AXI/AHB bus fabric and processor sub-systems.

Understanding of UPF and low-power design & implementation techniques.

Self-starter and willingness to learn.

Minimum Qualifications

Minimum requirement of a bachelors degree

Familiarity with the ASIC design flow.

Knowledge of digital design, SoC architecture, and HDL languages like Verilog.

Familiarity with design methodologies and industry standard EDA tools.

Pay & Benefits

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $122,700 and $214,300, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

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Refine Your Search

debug soc design engineer jobs in irvine, ca

Debug SoC Design Engineer

RFIC Design Engineer

Wireless SOC Verification Engineer

Wireless Design Verification Engineer

Digital Design Engineer (MPU)

Sr. Staff Design Verification Engineer

RFIC Test Engineer

Senior Staff Digital Design Engineer

Senior Staff Engineer, ASIC/VLSI Synthesis and Design

Wireless Systems Integration Engineer

Senior Staff Design Verification Engineer – PCIE/CXL Sub-System

Security Firmware Engineer

Senior Staff Design Engineer - PCIE/CXL Subsystem COE

Field Application Engineer – PowerPro

Wireless System Integration and Characterization Engineer

Senior Staff Engineer, ASIC Design/Implementation -- LEC/STA/Power Analysis

R&D Applications Engineer, Emulex Connectivity Division (ECD)

Principal Analog and Mixed-Signal IC Design Engineer

FPGA Verification Engineer, Air Vehicles

Sr. Full Chip Physical Verification Engineer (Silicon Engineering)

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