Top 58 Asic design engineer Jobs in Irvine, Ca

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ASIC Design Verification Engineer
Broadcom —Irvine, CA
- $129,400 - $207,000 a year
- Full-time
- 3 years
- Master's degree
- Bachelor's degree
- Employee stock purchase plan
- Paid holidays
ASIC Design Engineer
Broadcom —Irvine, CA
- $108,000 - $172,800 a year
- Full-time
- 6 years
- Master's degree
- Fair chance
- Employee stock purchase plan
- Paid holidays
Digital Design Engineer
Marvell —Irvine, CA
- $97,700 - $144,410 a year
- Full-time
- Mid-level
- 1 year
- Communication skills
- Employee stock purchase plan
8d
ASIC Design Engineer - Staff
Celero Communications, Inc. —Irvine, CA
- $150,000 - $250,000 a year
- 5 years
- Senior level
- Electrical Engineering
ASIC Design Engineer
Celero Communications, Inc. —Irvine, CA
- $150,000 - $250,000 a year
- Mid-level
- 3 years
- Electrical Engineering
Principal ASIC Design Engineer (Starshield)
SpaceX —Irvine, CA
- $200,000 - $285,000 a year
- Weekends as needed
- Computer science
- Computer Science
- 8 years
- Paid parental leave
- Employee stock purchase plan
Sr. ASIC Design Engineer (Starshield)
SpaceX —Irvine, CA
- $160,000 - $225,000 a year
- Weekends as needed
- Computer science
- Computer Science
- 5 years
- Paid parental leave
- Employee stock purchase plan
FPGA Design Engineer
Silvus Technologies —Irvine, CA
- $100,000 - $140,000 a year
- Monday to Friday
- Background check
- Computer science
- Computer Science
Quick Apply
R&D IC Design Engineer
Broadcom —Irvine, CA
- $141,300 - $226,000 a year
- Full-time
- 6 years
- Bachelor of Science
- Analysis skills
- Employee stock purchase plan
- Paid holidays
ATE Test Development Engineer
Broadcom —Irvine, CA
- $108,000 - $172,800 a year
- Full-time
- 6 years
- Master's degree
- Bachelor's degree
- Employee stock purchase plan
- Paid holidays
RTL Design Engineer (Silicon Engineering)
SpaceX —Irvine, CA
- $125,000 - $195,000 a year
- Extended hours
- Computer science
- Computer Science
- Mid-level
- Paid parental leave
- Employee stock purchase plan
Principal Physical Design Engineer
Celero Communications, Inc. —Irvine, CA
- $150,000 - $250,000 a year
- Schematics
- 11+ years
- Mentoring
Senior Staff Engineer, ASIC/VLSI Synthesis and Design
Marvell —Irvine, CA
- $135,900 - $201,130 a year
- Full-time
- Computer Science
- 5 years
- Master's degree
- Employee stock purchase plan
ASIC Verification Engineer
Broadcom —Irvine, CA
- $91,000 - $146,000 a year
- Full-time
- Mid-level
- 3 years
- Fair chance
- Employee stock purchase plan
- Paid holidays
Principal Engineer Digital Design
Infineon Technologies AG —Irvine, CA
- $175,300 - $241,000 a year
- Full-time
- Background check
- Pass drug screening
- 11+ years
Debug SoC Design Engineer
Apple —Irvine, CA
- $122,700 - $214,300 a year
- Bachelor's degree
- Senior level
- Employee stock purchase plan
- Health insurance
FPGA/ASIC Engineer
Red Digital Cinema, Inc. —Foothill Ranch, CA
- Computer Science
- Bachelor of Science
- Mid-level
Quick Apply
Wireless Design Verification Engineer
Apple —Irvine, CA
- $175,000 - $308,500 a year
- Bachelor of Science
- Analysis skills
- Bachelor's degree
- Employee stock purchase plan
- Health insurance
Staff Physical Design Engineer
Marvell —Irvine, CA
- $112,300 - $166,280 a year
- Full-time
- Computer Science
- Master's degree
- Analysis skills
- Employee stock purchase plan
RFIC Design Engineer (RFIC Engineering)
SpaceX —Irvine, CA
- $125,000 - $175,000 a year
- Weekends as needed
- Computer Science
- System design
- Mid-level
- Paid parental leave
- Employee stock purchase plan

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ASIC Design Verification Engineer

Broadcom -
Irvine, CA

Apply Now

Job Details

Full-time
$129,400 - $207,000 a year

Benefits

Employee stock purchase plan
Paid holidays
Health insurance
Dental insurance
Family leave
Employee assistance program
Vision insurance
401(k) matching
Paid sick time

Qualifications

Engineering development testing
Verification (System development task)
3 years
Master's degree
Collaboration with product development teams
Bachelor's degree
Doctor of Philosophy
Perl
SystemVerilog
Senior level
Leadership
Python

Full Job Description

Please Note:

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Job Description:

Would you like to become part of a stable team developing silicon products for Ethernet systems in the Cloud? Come join this team creating devices that accelerate AI/ML workflows! This team develops high throughput Ethernet solutions that deliver unprecedented performance at critically important power efficiency.

We are looking for highly skilled and efficient Constrained Random Design Verification engineers that want to verify new designs that can evolve rapidly at every generation in a very dynamic market using industry proven methodologies using System Verilog and UVM. You can become a member of an extremely skilled and efficient group of engineers.

This is a rare opportunity to be part of a team that leads products for a new line of devices. The candidate will work with our worldwide design and architecture teams to develop leading edge products. All aspects of Design Verification will be involved, along with opportunities for technical leadership.

Skills: Self motivated personality with a strong presence to do things right. Need to have a strong sense of teamwork and ability to work well with other. Constrained random verification methodologies with experience driving completion via coverage closure.

Preferable to have skills with SV and UVM, well versed in OOP

Tools/Languages: System Verilog (TB structures - Class, SVA, etc.), UVM, VCS, Incisive, Scripting skills a + (Python, Perl, ...)
Experience: Bachelors and 12+ years of related experience or Masters degree and 10+ years of related experience or PhD and 3+ years of related experience

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is $129,400.00 - $207,000.00.

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Apply Now

Refine Your Search

asic design engineer jobs in irvine, ca

ASIC Design Verification Engineer

ASIC Design Engineer

Digital Design Engineer

ASIC Design Engineer - Staff

ASIC Design Engineer

Principal ASIC Design Engineer (Starshield)

Sr. ASIC Design Engineer (Starshield)

FPGA Design Engineer

R&D IC Design Engineer

ATE Test Development Engineer

RTL Design Engineer (Silicon Engineering)

Principal Physical Design Engineer

Senior Staff Engineer, ASIC/VLSI Synthesis and Design

ASIC Verification Engineer

Principal Engineer Digital Design

Debug SoC Design Engineer

FPGA/ASIC Engineer

Wireless Design Verification Engineer

Staff Physical Design Engineer

RFIC Design Engineer (RFIC Engineering)

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