Top 1038 Simulation engineer Jobs in Livermore, Ca

Senior ASIC Design Verification Engineer
Cisco Systems —San Jose, CA
- $149,100 - $282,000 a year
- Full-time
- Master's degree
- Doctor of Philosophy
- US work authorization
- Paid parental leave
- Paid holidays
ASIC DFT Engineer
Cisco Systems, Inc. —San Jose, CA
- $125,300 - $186,800 a year
- Full-time
- CAD
- Master's degree
- Senior level
Quick Apply
ASIC Design Verification Engineer, Technical Leader
Cisco Systems —San Jose, CA
- $166,300 - $307,800 a year
- Full-time
- Office
- Master's degree
- 8 years
- Paid parental leave
- Paid holidays
Senior mixed-signal electrical engineer (Board Level)
ASML —San Jose, CA
- $165,375 - $275,625 a year
- Full-time
- Microsoft Excel
- 5 years
- Doctor of Philosophy
- Paid holidays
- Health insurance
Human Factors Engineer
Real Staffing —San Jose, CA
- $74,175 a year
- Product management
- Senior level
- Health savings account
- Disability insurance
Lead Electrical Design Engineer
Coherent Corp. —Fremont, CA
- Overtime
- 7 years
- Office
- Master's degree
High-Speed Photodetector Chip R&D Engineer
Vertilite Inc. —San Jose, CA
- $110,000 - $170,000 a year
- Full-time
- Hybrid work
- Background check
- Microsoft Excel
- Doctoral degree
- Relocation assistance
- Flexible schedule
Quick Apply
Design Verification Engineer (Einfochips)
Arrow Electronics, Inc. —San Jose, CA
- Full-time
- 6 years
- Office
- Travel
- Health savings account
- Disability insurance
ASIC Design Verification Technical Leader
Cisco Systems —San Jose, CA
- $166,300 - $307,800 a year
- Full-time
- 5 years
- Office
- Master's degree
- Paid parental leave
- Paid holidays
Optical Transceiver Engineer
Coherent Corp. —Fremont, CA
- Overtime
- CAD
- Bachelor of Science
- Writing skills
Senior Optical Transceiver Engineer
Coherent Corp. —Fremont, CA
- Overtime
- Bachelor of Science
- Writing skills
- Laboratory experience
Software Quality Assurance Engineer
ASML —San Jose, CA
- $103,125 - $151,250 a year
- Full-time
- Hybrid work
- Computer Science
- Office
- Analysis skills
- Paid holidays
- Health insurance
Electrical Engineer Signal Integrity and Power Integrity Technical Lead (7400)
Advantest —San Jose, CA
- $129,650 - $200,400 a year
- Full-time
- Background check
- Bachelor of Science
- System design
- Health insurance
- Dental insurance
Quick Apply
Sr. Principal Module Design Engineer
Coherent Corp. —Fremont, CA
- Overtime
- CAD
- Laboratory experience
- Office
Research scientist InP laser designer
Vertilite Inc. —San Jose, CA
- $87,527.47 - $164,513.50 a year
- Full-time
- Doctoral degree
- English
- Mid-level
- Health insurance
- Dental insurance
Quick Apply
ASIC Design Verification Engineer
Cisco Systems —San Jose, CA
- $146,700 - $277,600 a year
- Full-time
- Computer science
- Computer Science
- Master's degree
- Paid parental leave
- Paid holidays
Senior Thermal Engineering Technical Leader
Cisco Systems —San Jose, CA
- $179,000 - $328,600 a year
- Full-time
- System design
- 3 years
- Master's degree
- Paid parental leave
- Paid holidays
Staff Mechanical Engineer
Coherent Corp. —Fremont, CA
- Overtime
- Bachelor of Science
- Mid-level
- Office
ASIC Design Verification Engineer
Cisco Systems —San Jose, CA
- $138,100 - $256,000 a year
- Full-time
- Master's degree
- Bachelor's degree
- Doctor of Philosophy
- Paid parental leave
- Paid holidays
Mechanical Engineer: Accident Reconstruction
Talas Engineering —Hayward, CA
- $90,000 - $150,000 a year
- Overtime
- Hybrid work
- Bachelor of Science
- Mid-level
- 3 years
- Profit sharing
- Health savings account
Quick Apply

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simulation engineer jobs near livermore, ca

Senior ASIC Design Verification Engineer

Cisco Systems -
San Jose, CA

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Job Details

Full-time
$149,100 - $282,000 a year

Benefits

Paid parental leave
Paid holidays
Disability insurance
Health insurance
Dental insurance
401(k)
RSU
Parental leave
Vision insurance
401(k) matching
Life insurance

Qualifications

Engineering development testing
Verification (System development task)
Verilog
Debugging

Full Job Description

The application window is expected to close on: 10/01/2026Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

Meet the Team

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. As an ASIC Design Verification Engineer, you will play a critical role in developing Cisco’s revolutionary data center, AI networking solutions. Join us to power the future of the digital world.

Your Impact

Architect, develop, and maintain block, cluster, and top-level Design Verification environment infrastructure; Perform end-to-end verification of design blocks and top-level
Develop simulation models, test plans, direct and random tests, code or functional coverage, multi-chip/system simulation, post silicon bring up and performance analysis.
Ensure comprehensive verification coverage through code and functional coverage implementation and review
Collaborate with designers, architects, software teams, and vendors
Lead multiple tasks efficiently with clear written and verbal communication
Cultivate partnership and promote collaboration among team members

Minimum Qualifications:

Bachelor’s degree in Electrical or Computer engineering and 7+ years of ASIC related experience, or Master’s degree in Electrical or Computer engineering and 4+ years of ASIC related experience, or PhD in Electrical or Computer engineering + 1 year of ASIC related experience
Prior experience in System Verilog and UVM.
Experience with ASIC design and verification processes, debugging, methodology, and tools.
Experience in verifying blocks/clusters/full chip level for ASIC.

Preferred Qualifications:

Experience in PCIe and AXI protocol
Experience with Linux, C/C++, and/or Python/Perl.
Experience in Networking.
Experience with post-silicon lab bring-up

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.

Message to applicants applying to work in the U.S. and/or Canada:

The starting salary range posted for this position is $167,700.00 to $245,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.

U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:

10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer

For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.

Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:

.75% of incentive target for each 1% of revenue attainment up to 50% of quota;
1.5% of incentive target for each 1% of attainment between 50% and 75%;
1% of incentive target for each 1% of attainment between 75% and 100%; and
Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.

For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

The applicable full salary ranges for this position, by specific state, are listed below:

New York City Metro Area:
$167,700.00 - $282,000.00

Non-Metro New York state& Washington state:
$149,100.00 - $250,900.00

For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.

** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.

Apply Now

Refine Your Search

simulation engineer jobs in livermore, ca

Senior ASIC Design Verification Engineer

ASIC DFT Engineer

ASIC Design Verification Engineer, Technical Leader

Senior mixed-signal electrical engineer (Board Level)

Human Factors Engineer

Lead Electrical Design Engineer

High-Speed Photodetector Chip R&D Engineer

Design Verification Engineer (Einfochips)

ASIC Design Verification Technical Leader

Optical Transceiver Engineer

Senior Optical Transceiver Engineer

Software Quality Assurance Engineer

Electrical Engineer Signal Integrity and Power Integrity Technical Lead (7400)

Sr. Principal Module Design Engineer

Research scientist InP laser designer

ASIC Design Verification Engineer

Senior Thermal Engineering Technical Leader

Staff Mechanical Engineer

ASIC Design Verification Engineer

Mechanical Engineer: Accident Reconstruction

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