Top 484 Engineering lead Jobs in Milpitas, Ca

Lead Application Engineer (8146)
Advantest —San Jose, CA
- $129,000 - $200,000 a year
- Full-time
- Computer Science
- Software troubleshooting
- 5 years
- Health insurance
- Dental insurance
Quick Apply
Lead ASIC DFT Engineer
Cyient —San Jose, CA
- $80 - $85 an hour
- Full-time
- Analysis skills
- Mentoring
- In-person
Quick Apply
Hardware Lead Design Engineer
TMP Worldwide India Private Limited for ERS US —Milpitas, CA
- $83,000 - $128,000 a year
- Email
- Analysis skills
- In-person
- Senior level
- AD&D insurance
- Paid holidays
Quick Apply
Lead, Engineering Excellence
Bain & Co. —Palo Alto, CA
- $179,875 - $203,925 a year
- Full-time
- Hybrid work
- Azure
- Computer Science
- Office
- Wellness program
- Paid holidays
Quick Apply
Senior Staff Software Engineer, Integrations (Tech Lead) — Veza
ServiceNow —Santa Clara, CA
- $190,900 - $334,100 a year
- Online Application
- Hybrid work
- Azure
- 11+ years
- Office
- Employee stock purchase plan
- Health insurance
Quick Apply
Tools and Automations Lead, App Review
Apple —Cupertino, CA
- $149,200 - $249,000 a year
- Computer science
- 7 years
- Computer Science
- Employee stock purchase plan
- Health insurance
Leader, Customer Quality Engineering
Cisco Systems —San Jose, CA
- $166,800 - $272,700 a year
- Full-time
- Hybrid work
- Engineering
- US work authorization
- Manufacturing
- Paid parental leave
- Paid holidays
Leader, Hardware Engineering
Cisco Systems —San Jose, CA
- $176,100 - $323,600 a year
- Full-time
- Bachelor of Science
- Doctor of Philosophy
- Mentoring
- Paid parental leave
- Paid holidays
Mechanical Engineering Technical Leader
Cisco Systems —San Jose, CA
- $148,800 - $277,400 a year
- Full-time
- Master's degree
- Doctor of Philosophy
- US work authorization
- Paid parental leave
- Paid holidays
Hardware Engineering Technical Leader (hybrid) - 2014270
Cisco Systems —San Jose, CA
- $176,100 - $323,600 a year
- Full-time
- Hybrid work
- Office
- Master's degree
- Analysis skills
- Paid parental leave
- Paid holidays
Customer Operations Engineering Lead
Muon Space —San Jose, CA
- $127,000 - $187,000 a year
- Full-time
- Remote
- 7 years
- Analysis skills
- Mentoring
- Paid parental leave
- Paid holidays
Principal Engineering Lead
Arm —San Jose, CA
- $262,700 - $355,400 a year
- Email
- Office
- Mentoring
- US work authorization
ASIC DFT STA Technical Lead
Cisco Systems —San Jose, CA
- $148,800 - $277,400 a year
- Full-time
- 3 years
- Master's degree
- Analysis skills
- Paid parental leave
- Paid holidays
Energy Systems Support Engineering Lead
Tesla —Fremont, CA
- $120,800 - $307,200 a year
- Full-time
- Computer science
- Computer Science
- Mid-level
- Commuter assistance
- Health savings account
14d
SoC Verification Lead
NVIDIA —Santa Clara, CA
- $232,000 - $368,000 a year
- Full-time
- 11+ years
- Master's degree
- Experience equivalent to degree accepted
Quality Engineering Technical Leader
Cisco Systems —San Jose, CA
- $141,700 - $232,600 a year
- Full-time
- Hybrid work
- Engineering
- Master's degree
- 8 years
- Paid parental leave
- Paid holidays
13d
DFT Technical Leader
Cisco Systems —San Jose, CA
- $163,600 - $303,100 a year
- Full-time
- Hybrid work
- CAD
- Master's degree
- US work authorization
- Paid parental leave
- Paid holidays
Design Verification Engineering Lead - Silicon One
Cisco Systems —San Jose, CA
- $189,300 - $350,800 a year
- Full-time
- 5 years
- Master's degree
- Bachelor's degree
- Paid parental leave
- Paid holidays
Cross Functional Test Lead, Retail Engineering
Apple —Sunnyvale, CA
- $144,600 - $218,000 a year
- Computer science
- Computer Science
- 5 years
- Employee stock purchase plan
- Health insurance
Lead Integration Architect
Agilent Technologies Inc —Santa Clara, CA
- $153,040 - $286,950 a year
- Full-time
- System design
- Laboratory experience
- Senior level
3d

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Lead Application Engineer (8146)

Advantest -
San Jose, CA

Quick Apply

Job Details

Full-time
$129,000 - $200,000 a year

Benefits

Health insurance
Dental insurance
401(k)
Paid time off
Vision insurance
401(k) matching

Qualifications

Thermal analysis
Software engineering
Software troubleshooting
Thermal control
Electrical performance testing
Java
C++
Bachelor's degree
Computer hardware
Computer Engineering
Printed circuit board (PCB) layout
Engineering environmental testing
Electrical Engineering
Semiconductor experience
Hardware diagnostics
Debugging
Automated test equipment (ATE)

Full Job Description

About Advantest

Advantest America Inc. is part of Advantest Corporation, the world's largest provider of automated test equipment (ATE) for the semiconductor industry. The company designs and manufactures cutting-edge testing solutions that help semiconductor manufacturers ensure the quality and performance of their products. Advantest is known for innovation, reliability, and a strong commitment to supporting its customers and employees.

Our Purpose & Values:
Mission: Improve lives through advanced technologies and customer-focused innovation.
Vision: Be the most trusted and valued test solution provider in the semiconductor value chain.

Core Values:
I- Innovation is our Lifeblood
N- Number One is Our Aspiration
T- Trust is our Foundation
E- Empowerment is Our Motivation
G- Global is our Reach
R- Respect is our Heart
I - Inclusion and Diversity is Our Commitment
T- Teamwork is our Approach
Y- Yes is Our Attitude

Why Join Us:

At Advantest, innovation starts with people. We're looking for curious, capable, and collaborative individuals ready to shape the future of semiconductor technology. You'll join a global team where your ideas are valued, your growth is supported, and your work makes a real impact.

We foster an integrity-centered culture, where honesty, inclusion, and respect are the foundation of everything we do.Job Description

We are seeking a highly experienced Lead Application Engineer to join Advantest’s Research & Ventures (R&V) team, developing and delivering advanced semiconductor test solutions on the Advantest V93000 Test Platform, with a strong focus on wafer-level (die-level) testing, thermal management, and high-performance digital devices.

As part of the R&V team, you will have the opportunity to work on new and cutting-edge technologies and play a critical role in incubating, enabling, and bringing new products and capabilities to our customers. You will be a key technical contributor, working closely with R&D, cross-functional teams and customers to transform early concepts and advanced technologies into robust, scalable test solutions.

You will independently design, implement, debug, and optimize test programs for silicon devices at the wafer level, while managing the thermal and electrical challenges.

The ideal candidate is a self-starter with strong SmarTest8 expertise, hands-on experience with die-level probers, and a passion for innovation—capable of leading technical discussions, influencing research, and delivering end-to-end solutions that shape the future of semiconductor testing.

Responsibilities

Lead the design, development, execution, and debugging of test programs on the Advantest V93000 platform
Develop test programs, test methods, and reusable libraries using C++ and Java in SmarTest8
Own wafer-level (die-level) test program development, including silicon bring-up, characterization, and support using die-level probers
Manage and optimize thermal aspects of device testing, including temperature control strategies, thermal limitations, and correlation of electrical behavior across temperatures
Work with high-power devices and develop test programs that actively manage power dissipation and thermal constraints during testing, ensuring safe operation, test integrity, and repeatable results across operating conditions
Execute, debug, and resolve test program issues on both, offline and online systems
Provide end-to-end ownership of test solutions, spanning ATE hardware, probers, load boards, probe cards, and test software
Debug and resolve complex issues across hardware, software, silicon, and thermal domains
Act as the primary technical interface for cross-functional teams, leading technical discussions, design reviews, and root-cause analysis sessions
Support requirements analysis, benchmark testing, demonstrations, and training
Collaborate closely with R&D, COE, and global engineering teams to develop next-generation wafer-level and system-level test solutions
Partner with leading customers on next‑generation high‑power devices to co‑define advanced test requirements, exploring power delivery, thermal management, and wafer‑level test methodologies on the V93000 platform
Lead customer‑facing engagements—including technical discussions, deep‑dives, and pilot programs—to prototype and validate high‑power, thermally‑constrained test solutions, transforming early concepts into scalable test programs, methods, and reusable frameworks.

Requirements

Minimum Qualifications

Bachelor’s degree (or higher) in Electrical Engineering, Computer Engineering, Computer Science, or a related field
5–7 years of hands-on experience developing and debugging test programs, test methods, and libraries on V93000 using SmarTest8
Proficiency in Java for test program and test method development
Hands-on experience with wafer-level (die-level) testing, including working directly with silicon and dies using die-level probers
Proven experience managing thermal aspects of test devices, including temperature-dependent behavior and test execution across thermal conditions
Hands-on experience working with V93000 hardware, load boards, probe cards, and prober integration
Proven ability to debug and resolve issues end-to-end, spanning software, hardware, silicon, and thermal domains
Ability to lead technical discussions and influence technical decisions
Ability to work both independently and within a team in a fast-paced, changing environment
Self-motivated, proactive, and execution-focused

Preferred Skills

Experience developing test programs for digital and high-performance compute (HPC) devices
Deep understanding of V93000 system architecture, wafer-level test flows, and best practices
Strong understanding of high power devices and their thermal behavior at wafer level

Pay: $129,000.00 - $200,000.00 per year

Benefits:

401(k)
401(k) matching
Dental insurance
Health insurance
Paid time off
Vision insurance

Application Question(s):

Will you now or in the future require sponsorship for employment visa status?

Work Location: In person

Quick Apply

Refine Your Search

engineering lead jobs in milpitas, ca

Lead Application Engineer (8146)

Lead ASIC DFT Engineer

Hardware Lead Design Engineer

Lead, Engineering Excellence

Senior Staff Software Engineer, Integrations (Tech Lead) — Veza

Tools and Automations Lead, App Review

Leader, Customer Quality Engineering

Leader, Hardware Engineering

Mechanical Engineering Technical Leader

Hardware Engineering Technical Leader (hybrid) - 2014270

Customer Operations Engineering Lead

Principal Engineering Lead

ASIC DFT STA Technical Lead

Energy Systems Support Engineering Lead

SoC Verification Lead

Quality Engineering Technical Leader

DFT Technical Leader

Design Verification Engineering Lead - Silicon One

Cross Functional Test Lead, Retail Engineering

Lead Integration Architect

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