Top 105 Asic designer Jobs in Mountain View, Ca

Hardware Engineer, RTL
Normal Computing Corporation —Palo Alto, CA
- $200,000 - $400,000 a year
- Full-time
- Hybrid work
- Senior level
ASIC Design Engineer
Apple —Cupertino, CA
- Bachelor of Science
- Mid-level
- 3 years
11d
ASIC Design Engineer
NVIDIA —Santa Clara, CA
- $116,000 - $218,500 a year
- Full-time
- Computer science
- Computer Science
- Bachelor of Science
ASIC Verification Engineer
NVIDIA —Santa Clara, CA
- $116,000 - $218,500 a year
- Full-time
- Computer science
- Computer Science
- Research
GPU Verification Engineer - New College Grad 2026
NVIDIA —Santa Clara, CA
- $100,000 - $189,750 a year
- Full-time
- Computer science
- Computer Science
- Master's degree
5d
ASIC Design Engineer - Neural Engine DMA
Apple —Sunnyvale, CA
- $129,300 - $194,700 a year
- Bachelor's degree
- Entry level
- Under 1 year
- Employee stock purchase plan
- Health insurance
Senior ASIC Design Engineer
NVIDIA —Santa Clara, CA
- $136,000 - $264,500 a year
- Full-time
- Hybrid work
- Computer science
- Computer Science
- 5 years
Design Verification Engineer - SoC
Etched —San Jose, CA
- $150,000 - $275,000 a year
- Full-time
- Mid-level
- Office
- Analysis skills
- Health insurance
- Dental insurance
System Performance Modeling Engineer
Advanced Micro Devices, Inc —Santa Clara, CA
- Hybrid work
- Computer science
- Computer Science
- Software troubleshooting
Senior ASIC Verification Engineer - GPU
NVIDIA —Santa Clara, CA
- $196,000 - $310,500 a year
- Full-time
- 11+ years
- Master's degree
- Analysis skills
CPU DFT Verification Engineer
Apple —Santa Clara, CA
- $150,400 - $277,600 a year
- Bachelor of Science
- Mid-level
- 3 years
- Employee stock purchase plan
- Health insurance
Senior ASIC Verification Engineer
NVIDIA —Santa Clara, CA
- $168,000 - $310,500 a year
- Full-time
- Hybrid work
- 6 years
- Computer Science
- Analysis skills
STA/Constraints Engineer
Advanced Micro Devices, Inc —Santa Clara, CA
- Hybrid work
- CAD
- Writing skills
- English
RTL Power Optimization Engineer – New College Grad 2026
NVIDIA —Santa Clara, CA
- $116,000 - $218,500 a year
- Full-time
- Doctor of Philosophy
- Electrical Engineering
- Communication skills
SOC Verification and Methodology Engineer - SCL
Qualcomm —Santa Clara, CA
- $153,200 - $229,800 a year
- Engineering
- Doctor of Philosophy
- Senior level
Senior Software Engineer
Teradyne —San Jose, CA
- $177,900 - $277,400 a year
- 7 years
- Computer Science
- Software troubleshooting
- Paid holidays
- Disability insurance
Physical Design Engineer
Etched —San Jose, CA
- $200,000 - $300,000 a year
- Full-time
- 5 years
- Office
- Machine learning
- Health insurance
- Dental insurance
Camera Image Sensor Digital Design Engineer Lead
Apple —Cupertino, CA
- $175,500 - $311,700 a year
- Bachelor's degree
- Senior level
- 10 years
- Employee stock purchase plan
- Health insurance
Physical Design Engineer (Sunnyvale, CA)
Tachyum —Sunnyvale, CA
- $150,000 - $300,000 a year
- Computer Science
- 5 years
- Bachelor of Science
- Opportunities for advancement
Mempath Architect
Google —Mountain View, CA
- $240,000 - $333,000 a year
- Full-time
- Computer science
- Computer Science
- 11+ years
10d

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Hardware Engineer, RTL

Normal Computing Corporation
Palo Alto, CA

Apply Now

Job Details

Full-time
$200,000 - $400,000 a year

Qualifications

Verification (System development task)
Tooling
AI tools proficiency
Electronics design
System design for system development
SoC
Digital circuit design
Design engineering
Open source contribution
Engineering functional testing
SystemVerilog
Senior level
Debugging

Full Job Description

About Normal Computing

Normal Computing builds silicon that turns thermal noise from an obstacle into a computational resource. Conventional chips spend most of their energy forcing determinism onto physics; ours compute with it. Stochastic, in-memory, asynchronous: the result is 10-100× more AI inference per dollar, per watt.

We co-design the full stack: AI-native EDA systems in production with the world's largest semiconductor companies, and the advanced ASICs they make possible. Backed by $85M+ from the world's leading deep-tech investors and built by scientists, engineers, and operators from the labs that built modern computing.

Normal works as one team across New York, Silicon Valley, London, Copenhagen, and Seoul. We hire people who want the hardest version of their craft, across every discipline, at every seniority.

The Role

As an RTL Design Engineer at Normal, you will design and verify the digital logic at the heart of Normal's thermodynamic hardware. This work sits at the intersection of classical ASIC design, novel computing architectures, and a development environment where the hardware and the algorithms are built together, not in sequence.

You will own RTL from microarchitecture to tapeout: writing microarchitecture specifications, creating synthesizable SystemVerilog, working with design verification engineers fully test the design using conventional and formal methods, and working closely with physical design to make sure the design meets area and timing constraints. Because Normal's chips are not standard accelerators, the RTL engineer here is closer to first-principles decisions than at a larger company. You will be shaping architecture, not just implementing it.

This is a role for an engineer who collaborates effectively across teams, including architecture, verification and physical design. The strongest candidates have taped out silicon, written RTL and helped close coverage, and are comfortable working in an environment where the specification is still being developed in parallel.

What You Will Own

RTL Design: Write and own synthesizable RTL in SystemVerilog across blocks ranging from datapath logic to control and memory interfaces.
Microarchitecture: Work with architecture to translate high-level specifications into implementable microarchitectures.
Verification: Work closely with the verification team to review verification plans, assist on debug, and become a partner in closing coverage.
Physical Design Collaboration: Collaborate with physical design on timing closure, floorplanning constraints, and DFT.
Design Reviews: Participate in design reviews and contribute to architecture decisions, not just implementation.
Tapeout & Bring-up: Support tapeout preparation, integration, and post-silicon bring-up as needed.

What Makes You a Great Fit

Hands-on experience writing production RTL in SystemVerilog and closing it through synthesis and place-and-route
Experience in closing coverage to a high level
At least one tapeout in your background, from any node and any company size
Experience working on datapaths, pipelines, or custom logic where the microarchitecture was not fully specified upfront
Strong debugging instincts across simulation, waveforms, and formal counterexamples
Ability to work directly with architects and physical designers without needing a large intermediary layer
Industry experience in ASIC or SoC design

Bonus Points

Experience at an AI chip company where design and verification were tightly coupled
Open-source RTL contributions to projects like Chipyard, OpenTitan, or CVA6
Familiarity with RISC-V or other open ISAs
Experience with AI-assisted RTL or EDA tooling in your design workflow
Exposure to physical design constraints, floorplanning, or timing-driven RTL development

Equal Employment Opportunity Statement

Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.

Accessibility Accommodations

Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at [email protected].

Privacy Notice

By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.

Compensation Range: $200K - $400K

Apply Now

Refine Your Search

asic designer jobs in mountain view, ca

Hardware Engineer, RTL

ASIC Design Engineer

ASIC Design Engineer

ASIC Verification Engineer

GPU Verification Engineer - New College Grad 2026

ASIC Design Engineer - Neural Engine DMA

Senior ASIC Design Engineer

Design Verification Engineer - SoC

System Performance Modeling Engineer

Senior ASIC Verification Engineer - GPU

CPU DFT Verification Engineer

Senior ASIC Verification Engineer

STA/Constraints Engineer

RTL Power Optimization Engineer – New College Grad 2026

SOC Verification and Methodology Engineer - SCL

Senior Software Engineer

Physical Design Engineer

Camera Image Sensor Digital Design Engineer Lead

Physical Design Engineer (Sunnyvale, CA)

Mempath Architect

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