Top 865 Principal engineer, digital verification engineering Jobs in Phoenix, Az

Principal Engineer, Digital Verification Engineering
Analog Devices —Chandler, AZ
- Full-time
- Master's degree
- Analysis skills
- Doctor of Philosophy
Principal Software Engineer /Architect- PLM/Digital Engineering
Honeywell Aerospace —Phoenix, AZ
- Full-time
- 8 years
- Senior level
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Sr. Manufacturing Engineer
HELIGEAR ACQUISITION CO —Phoenix, AZ
- $98,300 - $163,800 a year
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- AD&D insurance
- Disability insurance
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Commissioning Engineer
Atlantach Technical Services —Chandler, AZ
- Full-time
- 5 years
- Engineering
- Mid-level
- Health insurance
- Dental insurance
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System Engineer- display systems
TMP Worldwide India Private Limited for ERS US —Phoenix, AZ
- $88,271.47 - $134,000.00 a year
- Email
- Hybrid work
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Advanced ASIC FPGA Verification Engineer for Crypto and Cross Domain Solutions
General Dynamics Mission Systems, Inc —Scottsdale, AZ
- $135,396 - $150,205 a year
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- 3 years
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Engineering Manager – Connection Design Services (JC654)
ilocatum —Tempe, AZ
- $130,000 - $170,000 a year
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- 401(k)
- Employee assistance program
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Principal PCB & Substrate Layout Engineer
Belcan —Phoenix, AZ
- $98 an hour
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- Health insurance
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Advanced ASIC FPGA Design Engineer for Crypto and Cross Domain Solutions
General Dynamics Mission Systems, Inc —Scottsdale, AZ
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Process Engineer- Waste Water treatment
Mentis Systems —Glendale, AZ
- Contract
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- 3 years
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5d
Avionics Software Engineer
Belcan —Phoenix, AZ
- $80,000 - $135,000 a year
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4d
Mobile Software Developer
Triumph Tech, LLC —Surprise, AZ
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3d
Senior FPGA Engineer
Belcan —Phoenix, AZ
- $130,000 - $180,000 a year
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- 5 years
- Senior level
- Electrical Engineering
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4d
Process Engineer (Korean bilingual required)
Timpl Careers Group, LLC —Phoenix, AZ
- $76,000 - $90,000 a year
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Sr Principal ASIC FPGA Engineer (Sign-on Bonus Available)
General Dynamics Mission Systems, Inc —Scottsdale, AZ
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- 8 years
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Systems Engineer (Avionics)
Experis —Phoenix, AZ
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12d
Senior Systems Engineer
General Dynamics Mission Systems, Inc —Scottsdale, AZ
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- 6 years
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Mass Properties Engineer with Active Secret Clearance
APR Consulting Inc —Chandler, AZ
- $45.42 an hour
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- Mid-level
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6d
Advanced ASIC FPGA Engineer- (Sign-on Bonus Available)
General Dynamics Mission Systems, Inc —Scottsdale, AZ
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Advanced Space Systems Engineer (Sign-on Bonus Available)
General Dynamics Mission Systems, Inc —Scottsdale, AZ
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- Full-time
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- Master's degree
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12d

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principal engineer, digital verification engineering jobs near phoenix, az

Principal Engineer, Digital Verification Engineering

Analog Devices -
Chandler, AZ

Apply Now

Job Details

Full-time

Qualifications

AI models
Content creation for technical audiences
Engineering development testing
Verification (System development task)
Technical documentation
Electronics test plan development
Verilog
Simulation tools
Technical writing experience within technology
Python

Full Job Description

About Analog Devices

Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X .

As a Principal Design Verification Engineer, you will own verification strategy and closure for complex analog and mixed-signal ICs, from verification planning through tape-out sign-off. You will drive the adoption of AI/ML techniques to improve regression efficiency, debug throughput, and coverage closure. Your work will span multiple business units, ensuring product quality and accelerating delivery across ADI's next-generation mixed-signal and power management products.

Key Responsibilities

Drive adoption of AI/ML methodologies for failure clustering, regression triage, anomaly detection, and intelligent coverage optimization
Define and own verification strategy, plans, and success metrics across block, top-level, and system contexts for mixed-signal ICs
Build and scale mixed-signal verification infrastructure including reusable SystemVerilog/UVM testbenches, monitors, scoreboards, and automated checkers
Lead functional coverage planning, closure analysis, and sign-off for tape-out readiness
Drive silicon correlation by comparing simulation expectations against lab measurements, refining models and tests based on measured behavior
Lead verification architecture and methodology reviews, influencing best practices across projects
Collaborate with design, applications, and test teams to ensure verification reflects real use-cases, operating modes, and corner scenarios

Required Skills and Experience

MSEE or MSCE with 10+ years of IC verification experience, or PhD with 8+ years (BSEE/BSCE with equivalent depth considered)
Expert-level proficiency in SystemVerilog and UVM with a track record of building coverage-driven verification environments for mixed-signal products
Track record of owning end-to-end verification readiness from planning through tape-out sign-off and production release
Strong Python scripting skills with experience applying AI/ML techniques to enhance verification productivity
Deep knowledge of formal verification, assertion-based methodology, and clock domain crossing analysis
Proficiency with Cadence verification tools: Xcelium (simulation), JasperGold (formal verification)
Excellent presentation, technical writing, and communication skills

Preferred Qualifications

Experience with mixed-signal and AMS verification techniques including Verilog-AMS, real-number modeling, and behavioral abstraction
Experience with gate-level simulation, SDF back-annotation, and post-layout verification
Background verifying power management and interface-rich mixed-signal devices across multiple power domains
Strong analytical and problem-solving abilities
Ability to work effectively in a collaborative team environment

Technical Scope

Development and deployment of AI/ML-driven workflows for regression analytics, failure classification, and debug acceleration
Full verification ownership from specification analysis through coverage closure and tape-out sign-off
Mixed-signal verification environment architecture including analog behavioral modeling and digital-analog interface checking
Verification methodology definition including test plan authoring, coverage model design, and regression management

Collaboration and Impact

Champion AI/ML-driven improvements to verification workflows, sharing results and best practices across teams
Partner with design, applications, and test teams to translate product requirements into verification coverage that reflects real operating conditions
Contribute to organizational knowledge through verification reviews, methodology forums, and cross-team technical exchanges

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

EEO is the Law: Notice of Applicant Rights Under the Law .

Job Req Type: Experienced

Required Travel: Yes, 10% of the time

Shift Type: 1st Shift/Days

Apply Now

Refine Your Search

principal engineer, digital verification engineering jobs in phoenix, az

Principal Engineer, Digital Verification Engineering

Principal Software Engineer /Architect- PLM/Digital Engineering

Sr. Manufacturing Engineer

Commissioning Engineer

System Engineer- display systems

Advanced ASIC FPGA Verification Engineer for Crypto and Cross Domain Solutions

Engineering Manager – Connection Design Services (JC654)

Principal PCB & Substrate Layout Engineer

Advanced ASIC FPGA Design Engineer for Crypto and Cross Domain Solutions

Process Engineer- Waste Water treatment

Avionics Software Engineer

Mobile Software Developer

Senior FPGA Engineer

Process Engineer (Korean bilingual required)

Sr Principal ASIC FPGA Engineer (Sign-on Bonus Available)

Systems Engineer (Avionics)

Senior Systems Engineer

Mass Properties Engineer with Active Secret Clearance

Advanced ASIC FPGA Engineer- (Sign-on Bonus Available)

Advanced Space Systems Engineer (Sign-on Bonus Available)

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