Top 1449 Lead engineer Jobs in Remote(us)

Lead ASIC DFT Engineer
Cyient —Remote
- From $100 an hour
- Full-time
- Remote
- Analysis skills
- Mentoring
- Senior level
Quick Apply
Lead System Engineer
CAI —Remote
- $70 - $75 an hour
- Full-time
- Remote
- 7 years
- Azure
- Supervising experience
- Health insurance
- Dental insurance
11d
Lead Flutter Engineer
goTenna —Remote
- $150,000 - $180,000 a year
- Full-time
- Remote
- Computer science
- Computer Science
- Bachelor's degree
- Paid holidays
- Disability insurance
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Engineer Lead
Ad Hoc —Remote
- $150,000 - $160,000 a year
- Full-time
- Remote
- Military encouraged
- Senior level
- Leadership
- Paid parental leave
- Dental insurance
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Lead Software Engineer, Backend
Cortex —Remote
- $215,000 - $245,000 a year
- Remote
- Computer science
- 7 years
- Computer Science
- Health insurance
- Dental insurance
Lead Millwork Engineer / Drafter
Micro-Cap Solutions —Remote
- $70,000 - $100,000 a year
- Full-time
- Supervising experience
- Continuous improvement
- Mentoring
- Health insurance
- 401(k)
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15h
Lead Substation Protection & Control Engineer
GAI Consultants Inc —Lisle, IL
- Remote
- Bachelor of Science
- Mentoring
- Senior level
- Paid holidays
- Disability insurance
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Ingénieur principal des applications/ Lead Application Engineer
GE Vernova —Boston, MA
- Full-time
- Remote
- Bachelor of Science
- Pass drug screening
- Product management
- Paid parental leave
- Paid holidays
Ingénieur principal des applications /Lead Application Engineer
GE Vernova —Boston, MA
- Full-time
- Remote
- Bachelor of Science
- Pass drug screening
- Product management
- Paid parental leave
- Paid holidays
Transmission Line Engineer (Mid, Senior, & Lead)
Leidos —Remote
- $73,450 - $132,775 a year
- Full-time
- Remote
- Engineering
- 8 years
- Analysis skills
- Referral program
Transmission Line Engineer (Mid, Senior, & Lead)
Leidos —Remote
- $73,450 - $132,775 a year
- Full-time
- Remote
- Engineering
- 8 years
- Analysis skills
- Referral program
Lead Software Engineer
Emergent Software —Kansas City, KS
- $140,000 - $160,000 a year
- Full-time
- Remote
- 5 years
- Java
- Mentoring
Quick Apply
6d
Artificial Intelligence Program Lead
Joint Technology Solution, Inc. —Remote
- Full-time
- Remote
- Computer science
- Azure
- Computer Science
- Health insurance
- Dental insurance
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GenAI Architect Lead
Brooksource —Nashville, TN
- $124,600 - $255,900 a year
- Contract
- Remote
- Computer Science
- 3 years
- AWS
- Health savings account
- Paid holidays
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Lead Software Engineer
Emergent Software —Austin, TX
- $140,000 - $160,000 a year
- Full-time
- Remote
- 5 years
- Java
- Mentoring
Quick Apply
6d
Lead Transmission Line Engineer
Leidos —Remote
- $92,300 - $166,850 a year
- Full-time
- Master's degree
- 8 years
- Travel
- Flexible schedule
Lead EPC Substation Project Engineer
Leidos —Remote
- $107,900 - $195,050 a year
- Full-time
- Remote
- Engineering
- System design
- Research
Lead Software Engineer
Emergent Software —Minneapolis, MN
- $140,000 - $160,000 a year
- Full-time
- Remote
- 5 years
- Java
- Mentoring
Quick Apply
6d
Software Engineer Team Lead
Emergent Staffing —Houston, TX
- $120,000 - $140,000 a year
- Full-time
- Remote
- System design
- SQL
- Supervising experience
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7d
Lead Prisma Cloud Security Engineer
Novacoast Staffing Services —Remote
- $150,000 - $180,000 a year
- Full-time
- Remote
- Background check
- Azure
- DevOps
- Health insurance
- Dental insurance
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Lead ASIC DFT Engineer

Cyient -
Remote

Quick Apply

Job Details

Full-time | Contract
From $100 an hour

Qualifications

Engineering development testing
Electronics functional testing
Integrated circuits (ICs)
Analysis skills
SoC
Digital circuit design
Product development
System architecture design
Simulation tools
Test analysis
Python
Debugging
Cross-functional communication

Full Job Description

Experience

Role Summary

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.

The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.

Key Responsibilities

Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
Act as a technical escalation point for advanced DFT and post-silicon debug issues.
Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.

Required Skills & Qualifications

Strong hands-on experience in ASIC DFT with end-to-end ownership.
Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
Experience with MBIST implementation and verification; SMS experience preferred.
Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
Proven post-silicon debug and silicon bring-up experience.
Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
Strong communication skills and the ability to work independently with minimal ramp-up.

Preferred Experience

MBIST post-silicon validation.
ATPG simulations and fault coverage debug.
DFT RTL, DFD, DFT verification, and IP-level DFT integration.
DFT SDC creation and DFT timing closure support.
Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
TCL/PERL scripting for DFT automation, reporting, and debug.
Experience working across multiple ASIC technology nodes and complex product development cycles.
Familiarity with yield learning, diagnosis, and manufacturing test optimization.

Pay: From $100.00 per hour

Work Location: Remote

Quick Apply

Refine Your Search

lead engineer jobs in remote(us)

Lead ASIC DFT Engineer

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Lead Flutter Engineer

Engineer Lead

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Lead Software Engineer

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Lead Transmission Line Engineer

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