Top 19 Dft engineer Jobs in Remote

Lead ASIC DFT Engineer
ZK Technologies —Remote
- $115,496.06 - $139,092.03 a year
- Contract
- Remote
- Analysis skills
- Mentoring
- Senior level
Quick Apply
Design for Test (DFT) Engineer, Principal
Positron AI —Remote
- $200,000 - $350,000 a year
- Full-time
- Remote
- Bachelor of Science
- 11+ years
- Analysis skills
Quick Apply
11d
DFT Engineer
Delos Data Inc —Palo Alto, CA
- $160,000 - $230,000 a year
- Full-time
- Remote
- 5 years
- Master's degree
- Analysis skills
- 401(k)
Quick Apply
PCB Layout Engineer
Keysight Technologies, Inc. —Calabasas, CA
- $114,620 - $191,030 a year
- Full-time
- Remote
- Schematics
- English
- Mid-level
- Health savings account
- Employee stock purchase plan
HL7 Interface Engineer - Cloverleaf - Remote
Software Technology Inc —Remote
- Remote
- Senior level
Quick Apply
7d
Senior Design Engineer (Remote)
Collins Aerospace —Columbia, SC
- $86,800 - $165,200 a year
- Full-time
- Remote
- 3 years
- Travel
- Mentoring
- Paid holidays
- Loan repayment program
13d
ASIC Design Verification Engineer
K2 Space —Remote
- $130,000 - $200,000 a year
- Remote
- Bachelor of Science
- 3 years
- Senior level
- Paid parental leave
- Health insurance
Principal Test Engineer/DFT Architect
Renesas Electronics —Austin, TX
- Full-time
- Remote
- 11+ years
- SQL
- Analysis skills
Quick Apply
HL7 Project Engineer (BILINGUAL: French and English with Emphasis in the areas of Radiology & Cardiology)
FUJIFILM —Remote
- $89.65 - $116,700.20 a year
- Remote
- Computer Science
- System design
- English
- Health insurance
- Dental insurance
Senior Associate - Semiconductor
Lumenci —Remote
- $80,000 - $120,000 a year
- Full-time
- Assembly
- Analysis skills
- Travel
- Health insurance
- Dental insurance
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Senior Digital Engineer
Renesas Electronics —Chandler, AZ
- Full-time
- Remote
- Computer Science
- 5 years
- English
Quick Apply
11d
Staff Engineer, Test
Renesas Electronics —San Jose, CA
- $140,000 - $175,000 a year
- Full-time
- Remote
- Master's degree
- 8 years
- Doctor of Philosophy
- Commuter assistance
- Health savings account
Quick Apply
Electrical/Firmware Engineer - Hardware Team (IoT + DoD Systems)
LMI —Remote
- $92,075 - $158,138 a year
- Full-time
- Remote
- 5 years
- Travel
- Linux
5d
Lead Embedded Electrical Engineer- US
Very LLC —New York, NY
- $100 an hour
- Remote
- Azure
- 6 years
- Bachelor of Science
Quick Apply
11d
Senior Staff Analog Design Engineer
Renesas Electronics —Chandler, AZ
- Full-time
- Remote
- English
- Travel
- Mentoring
Quick Apply
RFID Solutions & Mesh Firmware Engineer (RFID + IoT + DoD Systems)
LMI —Remote
- $100,000 - $190,000 a year
- Full-time
- Hybrid work
- Computer Science
- 5 years
- System design
5d
Principal Technical Leader for Automotive Systems Power
Renesas Electronics —Plano, TX
- Full-time
- Remote
- 11+ years
- Mentoring
- Senior level
Quick Apply
12d

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Design for Test (DFT) Engineer, Principal
Positron AI —Remote
As Principal DFT Engineer, you'll own DFT and DFx strategy end-to-end: defining the DFT architecture for our accelerators, integrating it into internal RTL and…
$200,000 - $350,000 a year
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11d
Principal Test Engineer/DFT Architect
Renesas Electronics —Austin, TX
The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas. ATE and Production Test Strategy.
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Lead ASIC DFT Engineer

ZK Technologies -
Remote

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Job Details

Contract
$115,496.06 - $139,092.03 a year

Qualifications

Engineering development testing
Electronics functional testing
Integrated circuits (ICs)
Analysis skills
SoC
Digital circuit design
System architecture design
Test analysis
Simulation analysis
Python
Debugging
Cross-functional communication

Full Job Description

Experience

10+ years of hands-on experience in ASIC Design-for-Test (DFT)

Role Summary

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.

The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.

Key Responsibilities

· Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.

· Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.

· Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.

· Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.

· Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.

· Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.

· Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.

· Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.

· Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.

· Act as a technical escalation point for advanced DFT and post-silicon debug issues.

· Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.

· Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.

Required Skills & Qualifications

· Strong hands-on experience in ASIC DFT with end-to-end ownership.

· Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.

· Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.

· Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.

· Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.

· Experience with MBIST implementation and verification; SMS experience preferred.

· Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.

· Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.

· Proven post-silicon debug and silicon bring-up experience.

· Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.

· Strong communication skills and the ability to work independently with minimal ramp-up.

Preferred Experience

· MBIST post-silicon validation.

· ATPG simulations and fault coverage debug.

· DFT RTL, DFD, DFT verification, and IP-level DFT integration.

· DFT SDC creation and DFT timing closure support.

· Boundary scan, iJTAG, SSN, and design-for-debug methodologies.

· TCL/PERL scripting for DFT automation, reporting, and debug.

· Experience working across multiple ASIC technology nodes and complex product development cycles.

· Familiarity with yield learning, diagnosis, and manufacturing test optimization.

Pay: $115,496.06 - $139,092.03 per year

Work Location: Remote

Quick Apply

Refine Your Search

dft engineer jobs in remote

Lead ASIC DFT Engineer

Design for Test (DFT) Engineer, Principal

DFT Engineer

PCB Layout Engineer

HL7 Interface Engineer - Cloverleaf - Remote

Senior Design Engineer (Remote)

ASIC Design Verification Engineer

Principal Test Engineer/DFT Architect

HL7 Project Engineer (BILINGUAL: French and English with Emphasis in the areas of Radiology & Cardiology)

Senior Associate - Semiconductor

Senior Digital Engineer

Staff Engineer, Test

Electrical/Firmware Engineer - Hardware Team (IoT + DoD Systems)

Lead Embedded Electrical Engineer- US

Senior Staff Analog Design Engineer

RFID Solutions & Mesh Firmware Engineer (RFID + IoT + DoD Systems)

Principal Technical Leader for Automotive Systems Power

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